src/amd/vulkan/radv_cs.c

@@ -186,8 +186,9 @@ gfx10_cs_emit_cache_flush(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level
          *sqtt_flush_bits |= RGP_FLUSH_FLUSH_CB | RGP_FLUSH_INVAL_CB;
       }
 
+      /* GFX11 can't flush DB_META and should use a TS event instead. */
       /* TODO: trigger on RADV_CMD_FLAG_FLUSH_AND_INV_DB_META ? */
-      if (gfx_level < GFX11 && (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB)) {
+      if (gfx_level != GFX11 && (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB)) {
          /* Flush HTILE. Will wait for idle later. */
          radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
          radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));

src/amd/vulkan/radv_formats.h

@@ -120,7 +120,7 @@ struct radv_physical_device;
 
 uint32_t radv_translate_buffer_numformat(const struct util_format_description *desc, int first_non_void);
 
-uint32_t radv_translate_tex_dataformat(const struct radv_physical_device *pdev, VkFormat format,
+uint32_t radv_translate_tex_dataformat(const struct radv_physical_device *pdev,
                                        const struct util_format_description *desc, int first_non_void);
 
 uint32_t radv_translate_tex_numformat(const struct util_format_description *desc, int first_non_void);

src/amd/vulkan/radv_image.h

@@ -299,9 +299,7 @@ radv_image_get_iterate256(const struct radv_device *device, struct radv_image *i
    const struct radv_physical_device *pdev = radv_device_physical(device);
 
    /* ITERATE_256 is required for depth or stencil MSAA images that are TC-compatible HTILE. */
-   return pdev->info.gfx_level >= GFX10 &&
-          (image->vk.usage & (VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT | VK_IMAGE_USAGE_TRANSFER_DST_BIT)) &&
-          radv_image_is_tc_compat_htile(image) && image->vk.samples > 1;
+   return pdev->info.gfx_level >= GFX10 && radv_image_is_tc_compat_htile(image) && image->vk.samples > 1;
 }
 
 bool radv_are_formats_dcc_compatible(const struct radv_physical_device *pdev, const void *pNext, VkFormat format,

src/amd/vulkan/radv_image_view.c

@@ -263,7 +263,7 @@ gfx6_make_texture_descriptor(struct radv_device *device, struct radv_image *imag
 
    num_format = radv_translate_tex_numformat(desc, first_non_void);
 
-   data_format = radv_translate_tex_dataformat(pdev, vk_format, desc, first_non_void);
+   data_format = radv_translate_tex_dataformat(pdev, desc, first_non_void);
    if (data_format == ~0) {
       data_format = 0;
    }

src/amd/vulkan/radv_physical_device.h

@@ -255,8 +255,6 @@ bool radv_enable_rt(const struct radv_physical_device *pdev, bool rt_pipelines);
 
 bool radv_emulate_rt(const struct radv_physical_device *pdev);
 
-bool radv_device_supports_etc(const struct radv_physical_device *pdev);
-
 uint32_t radv_find_memory_index(const struct radv_physical_device *pdev, VkMemoryPropertyFlags flags);
 
 VkResult create_null_physical_device(struct vk_instance *vk_instance);