src/amd/addrlib/inc/addrinterface.h

@@ -24,7 +24,7 @@ extern "C"
 #endif
 
 #define ADDRLIB_VERSION_MAJOR 9
-#define ADDRLIB_VERSION_MINOR 1
+#define ADDRLIB_VERSION_MINOR 3
 #define ADDRLIB_VERSION ((ADDRLIB_VERSION_MAJOR << 16) | ADDRLIB_VERSION_MINOR)
 
 /// Virtually all interface functions need ADDR_HANDLE as first parameter

src/amd/addrlib/src/amdgpu_asic_addr.h

@@ -104,6 +104,8 @@
 #define AMDGPU_GFX1151_RANGE    0xC0, 0xFF //# 192 <= x < 255
 #define AMDGPU_GFX1103_R1_RANGE 0x01, 0x80 //# 1 <= x < 128
 #define AMDGPU_GFX1103_R2_RANGE 0x80, 0xC0 //# 128 <= x < 192
+#define AMDGPU_GFX1103_R1X_RANGE 0xC0, 0xF0 //# 192 <= x < 240
+#define AMDGPU_GFX1103_R2X_RANGE 0xF0, 0xFF //# 240 <= x < 255
 
 #define AMDGPU_REMBRANDT_RANGE  0x01, 0xFF //# 01 <= x < 255
 #define AMDGPU_RAPHAEL_RANGE    0x01, 0xFF //# 1 <= x < max
@@ -179,6 +181,8 @@
 #define ASICREV_IS_GFX1151(r)          ASICREV_IS(r, GFX1151)
 #define ASICREV_IS_GFX1103_R1(r)       ASICREV_IS(r, GFX1103_R1)
 #define ASICREV_IS_GFX1103_R2(r)       ASICREV_IS(r, GFX1103_R2)
+#define ASICREV_IS_GFX1103_R1X(r)      ASICREV_IS(r, GFX1103_R1X)
+#define ASICREV_IS_GFX1103_R2X(r)      ASICREV_IS(r, GFX1103_R2X)
 
 #define ASICREV_IS_REMBRANDT(r)        ASICREV_IS(r, REMBRANDT)
 #define ASICREV_IS_RAPHAEL(r)          ASICREV_IS(r, RAPHAEL)

src/amd/addrlib/src/core/addrlib3.cpp

@@ -321,6 +321,8 @@ ADDR_E_RETURNCODE Lib::ComputeSurfaceInfo(
                     }
                 }
             }
+
+            SetEquationIndex(&localIn, pOut);
         }
     }
 
@@ -365,6 +367,7 @@ ADDR_E_RETURNCODE Lib::GetPossibleSwizzleModes(
         {
             pOut->validModes.swLinear = 1;
         }
+
         // Depth/Stencil images can't be linear and must be 2D swizzle modes.
         // These three are related to DB block that supports only SW_64KB_2D and SW_256KB_2D for DSV.
         else if (flags.depth || flags.stencil)
@@ -772,8 +775,8 @@ ADDR_E_RETURNCODE Lib::ComputeSubResourceOffsetForSwizzlePattern(
     ADDR_E_RETURNCODE returnCode = ADDR_OK;
 
     if ((GetFillSizeFieldsFlags() == TRUE) &&
-        ((pIn->size  != sizeof(ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT)) ||
-         (pOut->size != sizeof(ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT))))
+        ((pIn->size  != sizeof(ADDR3_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT)) ||
+         (pOut->size != sizeof(ADDR3_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT))))
     {
         returnCode = ADDR_INVALIDPARAMS;
     }

src/amd/addrlib/src/core/addrlib3.h

@@ -335,7 +335,9 @@ protected:
         return GetBlockSize(swizzleMode) > 256u;
     }
 
-    virtual UINT_32 HwlComputeMaxBaseAlignments() const  { return 256 * 1024; }
+    // The max alignment is tied to the swizzle mode and since the largest swizzle mode is 256kb, so the maximal
+    // alignment is also 256kb.
+    virtual UINT_32 HwlComputeMaxBaseAlignments() const  { return 262144u; }
 
     virtual BOOL_32 HwlInitGlobalParams(const ADDR_CREATE_INPUT* pCreateIn)
     {
@@ -410,6 +412,28 @@ protected:
         return ADDR_NOTSUPPORTED;
     }
 
+    virtual UINT_32 HwlGetEquationIndex(
+        const ADDR3_COMPUTE_SURFACE_INFO_INPUT* pIn) const
+    {
+        ADDR_NOT_IMPLEMENTED();
+        return ADDR_INVALID_EQUATION_INDEX;
+    }
+
+    void SetEquationIndex(
+        const ADDR3_COMPUTE_SURFACE_INFO_INPUT* pIn,
+        ADDR3_COMPUTE_SURFACE_INFO_OUTPUT*      pOut) const
+    {
+        UINT_32 equationIdx = HwlGetEquationIndex(pIn);
+
+        if (pOut->pMipInfo != NULL)
+        {
+            for (UINT_32 i = 0; i < pIn->numMipLevels; i++)
+            {
+                pOut->pMipInfo[i].equationIndex = equationIdx;
+            }
+        }
+    }
+
     ADDR_E_RETURNCODE ApplyCustomizedPitchHeight(
         const ADDR3_COMPUTE_SURFACE_INFO_INPUT* pIn,
         ADDR3_COMPUTE_SURFACE_INFO_OUTPUT*      pOut) const;

src/amd/addrlib/src/gfx11/gfx11addrlib.cpp

@@ -739,11 +739,8 @@ ChipFamily Gfx11Lib::HwlConvertChipFamily(
             {
             }
             break;
+
         case FAMILY_GFX1150:
-            if  (false
-                 || ASICREV_IS_GFX1150(chipRevision)
-                 || ASICREV_IS_GFX1151(chipRevision)
-                )
             {
                 m_settings.isGfx1150 = 1;
             }
@@ -3468,7 +3465,7 @@ ADDR_E_RETURNCODE Gfx11Lib::ComputeSurfaceInfoMacroTiled(
                 if (IsZOrderSwizzle(pIn->swizzleMode) && (index <= 1))
                 {
                     fixedTailMaxDim.w /= Block256_2d[index].w / Block256_2d[2].w;
-                    fixedTailMaxDim.h /= Block256_2d[index].w / Block256_2d[2].w;
+                    fixedTailMaxDim.h /= Block256_2d[index].h / Block256_2d[2].h;
                 }
 
                 for (UINT_32 i = 0; i < pIn->numMipLevels; i++)

src/amd/addrlib/src/gfx12/gfx12addrlib.cpp

@@ -219,6 +219,36 @@ VOID Gfx12Lib::InitEquationTable()
     }
 }
 
+/**
+************************************************************************************************************************
+*   Gfx12Lib::HwlGetEquationIndex
+*
+*   @brief
+*       Return equationIndex by surface info input
+*
+*   @return
+*       equationIndex
+************************************************************************************************************************
+*/
+UINT_32 Gfx12Lib::HwlGetEquationIndex(
+    const ADDR3_COMPUTE_SURFACE_INFO_INPUT* pIn    ///< [in] input structure
+    ) const
+{
+    UINT_32 equationIdx = ADDR_INVALID_EQUATION_INDEX;
+
+    if ((pIn->resourceType == ADDR_RSRC_TEX_2D) ||
+        (pIn->resourceType == ADDR_RSRC_TEX_3D))
+    {
+        const UINT_32 swMode   = static_cast<UINT_32>(pIn->swizzleMode);
+        const UINT_32 msaaIdx  = Log2(pIn->numSamples);
+        const UINT_32 elemLog2 = Log2(pIn->bpp >> 3);
+
+        equationIdx = m_equationLookupTable[swMode][msaaIdx][elemLog2];
+    }
+
+    return equationIdx;
+}
+
 /**
 ************************************************************************************************************************
 *   Gfx12Lib::InitBlockDimensionTable
@@ -1471,7 +1501,6 @@ void Gfx12Lib::SanityCheckSurfSize(
 #endif
 }
 
-
 /**
 ************************************************************************************************************************
 *   Gfx12Lib::HwlCalcBlockSize

src/amd/addrlib/src/gfx12/gfx12addrlib.h

@@ -87,6 +87,9 @@ protected:
         const ADDR3_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn,
         ADDR3_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT*      pOut) const override;
 
+    virtual UINT_32 HwlGetEquationIndex(
+        const ADDR3_COMPUTE_SURFACE_INFO_INPUT* pIn) const override;
+
     virtual UINT_32 HwlGetEquationTableInfo(const ADDR_EQUATION** ppEquationTable) const override
     {
         *ppEquationTable = m_equationTable;

src/amd/ci/angle-radv-stoney-aco-fails.txt

@@ -8,12 +8,6 @@
 KHR-GLES31.core.geometry_shader.rendering.rendering.triangles_with_adjacency_input_line_strip_output_triangle_strip_adjacency_drawcall,Fail
 KHR-GLES31.core.geometry_shader.rendering.rendering.triangles_with_adjacency_input_triangle_strip_output_triangle_strip_adjacency_drawcall,Fail
 
-# ANGLE passes depthBiasConstantFactor directly to GlobalDepthOffsetConstant, while zink multiplies by 2.0.
-# radeonsi has an extra 2.0 factor in the 16-bit depth case vs 24-bit, which radv doesn't have.
-# I expect this is a radv bug due to missing VK CTS coverage:
-# https://gitlab.khronos.org/Tracker/vk-gl-cts/-/issues/4169
-dEQP-GLES3.functional.polygon_offset.fixed16_render_with_units,Fail
-
 # Failure in later miplevels, occasionally flaky
 dEQP-GLES3.functional.texture.specification.teximage2d_depth.depth_component24,Fail
 dEQP-GLES3.functional.texture.specification.teximage2d_depth.depth24_stencil8,Fail

src/amd/ci/gitlab-ci-inc.yml

@@ -238,6 +238,7 @@
     MESA_VK_IGNORE_CONFORMANCE_WARNING: 1
     # Enable ETC2 emulation on non-native platforms (RENOIR,RDNA+, GFX6-8 dGPUs)
     radv_require_etc2: 'true'
+    B2C_JOB_WARN_REGEX: '\*ERROR\* ring .* timeout'
 
 .b2c-test-radv-vk:
   extends:

src/amd/ci/radv-navi10-aco-flakes.txt

@@ -7,6 +7,7 @@ dEQP-VK.pipeline.fast_linked_library.depth.nocolor.format.d16_unorm_s8_uint_sepa
 dEQP-VK.query_pool.statistics_query.host_query_reset.geometry_shader_(invocations|primitives).secondary.(32|64)bits_.*
 
 # New CTS flakes in 1.3.8.0
+dEQP-VK.api.copy_and_blit.sparse.image_to_image.simple_tests.partial_image
 dEQP-VK.api.copy_and_blit.sparse.image_to_image.simple_tests.partial_image_npot_diff_format_clear
 dEQP-VK.api.copy_and_blit.sparse.image_to_image.simple_tests.partial_image_npot_diff_format_noclear
 dEQP-VK.api.copy_and_blit.sparse.image_to_image.simple_tests.partial_image_npot_same_format_clear
@@ -14,4 +15,5 @@ dEQP-VK.api.copy_and_blit.sparse.image_to_image.simple_tests.partial_image_npot_
 dEQP-VK.api.copy_and_blit.sparse.image_to_image.simple_tests.partial_image_pot_diff_format_clear
 dEQP-VK.api.copy_and_blit.sparse.image_to_image.simple_tests.partial_image_pot_diff_format_noclear
 dEQP-VK.api.copy_and_blit.sparse.image_to_image.simple_tests.partial_image_pot_same_format_clear
+dEQP-VK.api.copy_and_blit.sparse.image_to_image.simple_tests.whole_image
 dEQP-VK.api.copy_and_blit.sparse.image_to_image.simple_tests.whole_image_diff_format

src/amd/ci/radv-navi21-aco-flakes.txt

@@ -24,3 +24,8 @@ dEQP-VK.ray_tracing_pipeline.pipeline_no_null_shaders_flag.misc.miss_maintenance
 dEQP-VK.api.copy_and_blit.sparse.image_to_image.simple_tests.partial_image
 dEQP-VK.api.copy_and_blit.sparse.image_to_image.simple_tests.partial_image_pot_same_format_clear
 dEQP-VK.api.copy_and_blit.sparse.image_to_image.simple_tests.partial_image_pot_same_format_noclear
+dEQP-VK.api.copy_and_blit.sparse.image_to_image.simple_tests.whole_image
+
+dEQP-VK.draw.dynamic_rendering.partial_secondary_cmd_buff.scissor.dynamic_scissor_updates_between_draws
+dEQP-VK.subgroups.clustered.framebuffer.subgroupclusteredmin_int8_t_tess_control
+dEQP-VK.texture.filtering.cube.sizes.64x64.nearest

src/amd/ci/radv-navi31-aco-flakes.txt

@@ -14,3 +14,6 @@ dEQP-VK.api.copy_and_blit.sparse.image_to_image.simple_tests.partial_image_pot_d
 dEQP-VK.api.copy_and_blit.sparse.image_to_image.simple_tests.partial_image_pot_same_format_noclear
 dEQP-VK.api.copy_and_blit.sparse.image_to_image.simple_tests.partial_image_npot_same_format_clear
 dEQP-VK.api.copy_and_blit.sparse.image_to_image.simple_tests.partial_image_pot_same_format_clear
+dEQP-VK.api.copy_and_blit.sparse.image_to_image.simple_tests.whole_image
+
+dEQP-VK.renderpass2.dedicated_allocation.attachment_allocation.input_output.71

src/amd/ci/radv-vega10-aco-flakes.txt

@@ -2,4 +2,5 @@
 dEQP-VK.api.copy_and_blit.sparse.image_to_image.simple_tests.partial_image
 dEQP-VK.api.copy_and_blit.sparse.image_to_image.simple_tests.partial_image_npot_same_format_clear
 dEQP-VK.api.copy_and_blit.sparse.image_to_image.simple_tests.partial_image_pot_diff_format_clear
+dEQP-VK.api.copy_and_blit.sparse.image_to_image.simple_tests.whole_image
 dEQP-VK.api.copy_and_blit.sparse.image_to_image.simple_tests.whole_image_diff_format

src/amd/common/ac_descriptors.h

@@ -113,6 +113,11 @@ struct ac_buffer_state {
    uint32_t gfx10_oob_select : 2;
 };
 
+void
+ac_set_buf_desc_word3(const enum amd_gfx_level gfx_level,
+                      const struct ac_buffer_state *state,
+                      uint32_t *rsrc_word3);
+
 void
 ac_build_buffer_descriptor(const enum amd_gfx_level gfx_level,
                            const struct ac_buffer_state *state,
@@ -128,8 +133,141 @@ void
 ac_build_attr_ring_descriptor(const enum amd_gfx_level gfx_level,
                               uint64_t va,
                               uint32_t size,
+                              uint32_t stride,
                               uint32_t desc[4]);
 
+struct ac_ds_state {
+   const struct radeon_surf *surf;
+   uint64_t va;
+   enum pipe_format format;
+   uint32_t width : 17;
+   uint32_t height : 17;
+   uint32_t level : 5;
+   uint32_t num_levels : 6;
+   uint32_t num_samples : 5;
+   uint32_t first_layer : 14;
+   uint32_t last_layer : 14;
+
+   uint32_t allow_expclear : 1;
+   uint32_t stencil_only : 1;
+   uint32_t z_read_only : 1;
+   uint32_t stencil_read_only : 1;
+
+   uint32_t htile_enabled : 1;
+   uint32_t htile_stencil_disabled : 1;
+   uint32_t vrs_enabled : 1;
+};
+
+struct ac_ds_surface {
+   uint64_t db_depth_base;
+   uint64_t db_stencil_base;
+   uint32_t db_depth_view;
+   uint32_t db_depth_size;
+   uint32_t db_z_info;
+   uint32_t db_stencil_info;
+
+   union {
+      struct {
+         uint64_t hiz_base;
+         uint32_t hiz_info;
+         uint32_t hiz_size_xy;
+         uint64_t his_base;
+         uint32_t his_info;
+         uint32_t his_size_xy;
+         uint32_t db_depth_view1;
+      } gfx12;
+
+      struct {
+         uint64_t db_htile_data_base;
+         uint32_t db_depth_info;
+         uint32_t db_depth_slice;
+         uint32_t db_htile_surface;
+         uint32_t db_z_info2;
+         uint32_t db_stencil_info2;
+      } gfx6;
+   } u;
+};
+
+void
+ac_init_ds_surface(const struct radeon_info *info, const struct ac_ds_state *state, struct ac_ds_surface *ds);
+
+struct ac_mutable_ds_state {
+   const struct ac_ds_surface *ds; /* original DS surface */
+   enum pipe_format format;
+   uint32_t tc_compat_htile_enabled : 1;
+   uint32_t zrange_precision : 1;
+   uint32_t no_d16_compression : 1;
+};
+
+void
+ac_set_mutable_ds_surface_fields(const struct radeon_info *info, const struct ac_mutable_ds_state *state,
+                                 struct ac_ds_surface *ds);
+
+struct ac_cb_state {
+   const struct radeon_surf *surf;
+   enum pipe_format format;
+   uint32_t width : 17;
+   uint32_t height : 17;
+   uint32_t first_layer : 14;
+   uint32_t last_layer : 14;
+   uint32_t num_layers : 14;
+   uint32_t num_samples : 5;
+   uint32_t num_storage_samples : 5;
+   uint32_t base_level : 5;
+   uint32_t num_levels : 6;
+
+   struct {
+      struct ac_surf_nbc_view *nbc_view;
+   } gfx10;
+};
+
+struct ac_cb_surface {
+   uint32_t cb_color_info;
+   uint32_t cb_color_view;
+   uint32_t cb_color_view2;
+   uint32_t cb_color_attrib;
+   uint32_t cb_color_attrib2; /* GFX9+ */
+   uint32_t cb_color_attrib3; /* GFX10+ */
+   uint32_t cb_dcc_control;
+   uint64_t cb_color_base;
+   uint64_t cb_color_cmask;
+   uint64_t cb_color_fmask;
+   uint64_t cb_dcc_base;
+   uint32_t cb_color_slice;
+   uint32_t cb_color_cmask_slice;
+   uint32_t cb_color_fmask_slice;
+   union {
+      uint32_t cb_color_pitch; /* GFX6-GFX8 */
+      uint32_t cb_mrt_epitch;  /* GFX9+ */
+   };
+};
+
+void
+ac_init_cb_surface(const struct radeon_info *info, const struct ac_cb_state *state, struct ac_cb_surface *cb);
+
+struct ac_mutable_cb_state {
+   const struct radeon_surf *surf;
+   const struct ac_cb_surface *cb; /* original CB surface */
+   uint64_t va;
+
+   uint32_t base_level : 5;
+   uint32_t num_samples : 5;
+
+   uint32_t fmask_enabled : 1;
+   uint32_t cmask_enabled : 1;
+   uint32_t fast_clear_enabled : 1;
+   uint32_t tc_compat_cmask_enabled : 1;
+   uint32_t dcc_enabled : 1;
+
+   struct {
+      struct ac_surf_nbc_view *nbc_view;
+   } gfx10;
+};
+
+void
+ac_set_mutable_cb_surface_fields(const struct radeon_info *info, const struct ac_mutable_cb_state *state,
+                                 struct ac_cb_surface *cb);
+
 #ifdef __cplusplus
 }
 #endif

src/amd/common/ac_formats.c

@@ -5,6 +5,7 @@
  * SPDX-License-Identifier: MIT
  */
 
+#include "ac_gpu_info.h"
 #include "ac_formats.h"
 #include "ac_gpu_info.h"
 
@@ -194,6 +195,255 @@ ac_translate_tex_numformat(const struct util_format_description *desc,
    return num_format;
 }
 
+uint32_t
+ac_translate_tex_dataformat(const struct radeon_info *info,
+                            const struct util_format_description *desc,
+                            int first_non_void)
+{
+   bool uniform = true;
+   int i;
+
+   /* Colorspace (return non-RGB formats directly). */
+   switch (desc->colorspace) {
+   /* Depth stencil formats */
+   case UTIL_FORMAT_COLORSPACE_ZS:
+      switch (desc->format) {
+      case PIPE_FORMAT_Z16_UNORM:
+         return V_008F14_IMG_DATA_FORMAT_16;
+      case PIPE_FORMAT_X24S8_UINT:
+      case PIPE_FORMAT_S8X24_UINT:
+         /*
+          * Implemented as an 8_8_8_8 data format to fix texture
+          * gathers in stencil sampling. This affects at least
+          * GL45-CTS.texture_cube_map_array.sampling on GFX8.
+          */
+         if (info->gfx_level <= GFX8)
+            return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
+
+         if (desc->format == PIPE_FORMAT_X24S8_UINT)
+            return V_008F14_IMG_DATA_FORMAT_8_24;
+         else
+            return V_008F14_IMG_DATA_FORMAT_24_8;
+      case PIPE_FORMAT_Z24X8_UNORM:
+      case PIPE_FORMAT_Z24_UNORM_S8_UINT:
+         return V_008F14_IMG_DATA_FORMAT_8_24;
+      case PIPE_FORMAT_X8Z24_UNORM:
+      case PIPE_FORMAT_S8_UINT_Z24_UNORM:
+         return V_008F14_IMG_DATA_FORMAT_24_8;
+      case PIPE_FORMAT_S8_UINT:
+         return V_008F14_IMG_DATA_FORMAT_8;
+      case PIPE_FORMAT_Z32_FLOAT:
+         return V_008F14_IMG_DATA_FORMAT_32;
+      case PIPE_FORMAT_X32_S8X24_UINT:
+      case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
+         return V_008F14_IMG_DATA_FORMAT_X24_8_32;
+      default:
+         return ~0;
+      }
+
+   case UTIL_FORMAT_COLORSPACE_YUV:
+      return ~0; /* TODO */
+
+   default:
+      break;
+   }
+
+   if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
+      switch (desc->format) {
+      case PIPE_FORMAT_RGTC1_SNORM:
+      case PIPE_FORMAT_LATC1_SNORM:
+      case PIPE_FORMAT_RGTC1_UNORM:
+      case PIPE_FORMAT_LATC1_UNORM:
+         return V_008F14_IMG_DATA_FORMAT_BC4;
+      case PIPE_FORMAT_RGTC2_SNORM:
+      case PIPE_FORMAT_LATC2_SNORM:
+      case PIPE_FORMAT_RGTC2_UNORM:
+      case PIPE_FORMAT_LATC2_UNORM:
+         return V_008F14_IMG_DATA_FORMAT_BC5;
+      default:
+         return ~0;
+      }
+   }
+
+   if (desc->layout == UTIL_FORMAT_LAYOUT_ETC) {
+      switch (desc->format) {
+      case PIPE_FORMAT_ETC1_RGB8:
+      case PIPE_FORMAT_ETC2_RGB8:
+      case PIPE_FORMAT_ETC2_SRGB8:
+         return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
+      case PIPE_FORMAT_ETC2_RGB8A1:
+      case PIPE_FORMAT_ETC2_SRGB8A1:
+         return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
+      case PIPE_FORMAT_ETC2_RGBA8:
+      case PIPE_FORMAT_ETC2_SRGBA8:
+         return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
+      case PIPE_FORMAT_ETC2_R11_UNORM:
+      case PIPE_FORMAT_ETC2_R11_SNORM:
+         return V_008F14_IMG_DATA_FORMAT_ETC2_R;
+      case PIPE_FORMAT_ETC2_RG11_UNORM:
+      case PIPE_FORMAT_ETC2_RG11_SNORM:
+         return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
+      default:
+         break;
+      }
+   }
+
+   if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
+      switch (desc->format) {
+      case PIPE_FORMAT_BPTC_RGBA_UNORM:
+      case PIPE_FORMAT_BPTC_SRGBA:
+         return V_008F14_IMG_DATA_FORMAT_BC7;
+      case PIPE_FORMAT_BPTC_RGB_FLOAT:
+      case PIPE_FORMAT_BPTC_RGB_UFLOAT:
+         return V_008F14_IMG_DATA_FORMAT_BC6;
+      default:
+         return ~0;
+      }
+   }
+
+   if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
+      switch (desc->format) {
+      case PIPE_FORMAT_R8G8_B8G8_UNORM:
+      case PIPE_FORMAT_G8R8_B8R8_UNORM:
+      case PIPE_FORMAT_B8G8_R8G8_UNORM:
+         return V_008F14_IMG_DATA_FORMAT_GB_GR;
+      case PIPE_FORMAT_G8R8_G8B8_UNORM:
+      case PIPE_FORMAT_R8G8_R8B8_UNORM:
+      case PIPE_FORMAT_G8B8_G8R8_UNORM:
+         return V_008F14_IMG_DATA_FORMAT_BG_RG;
+      default:
+         return ~0;
+      }
+   }
+
+   if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
+      switch (desc->format) {
+      case PIPE_FORMAT_DXT1_RGB:
+      case PIPE_FORMAT_DXT1_RGBA:
+      case PIPE_FORMAT_DXT1_SRGB:
+      case PIPE_FORMAT_DXT1_SRGBA:
+         return V_008F14_IMG_DATA_FORMAT_BC1;
+      case PIPE_FORMAT_DXT3_RGBA:
+      case PIPE_FORMAT_DXT3_SRGBA:
+         return V_008F14_IMG_DATA_FORMAT_BC2;
+      case PIPE_FORMAT_DXT5_RGBA:
+      case PIPE_FORMAT_DXT5_SRGBA:
+         return V_008F14_IMG_DATA_FORMAT_BC3;
+      default:
+         return ~0;
+      }
+   }
+
+   if (desc->format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
+      return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
+   } else if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT) {
+      return V_008F14_IMG_DATA_FORMAT_10_11_11;
+   }
+
+   /* hw cannot support mixed formats (except depth/stencil, since only
+    * depth is read).*/
+   if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
+      return ~0;
+
+   if (first_non_void < 0 || first_non_void > 3)
+      return ~0;
+
+   /* See whether the components are of the same size. */
+   for (i = 1; i < desc->nr_channels; i++) {
+      uniform = uniform && desc->channel[0].size == desc->channel[i].size;
+   }
+
+   /* Non-uniform formats. */
+   if (!uniform) {
+      switch (desc->nr_channels) {
+      case 3:
+         if (desc->channel[0].size == 5 && desc->channel[1].size == 6 &&
+             desc->channel[2].size == 5) {
+            return V_008F14_IMG_DATA_FORMAT_5_6_5;
+         }
+         return ~0;
+      case 4:
+         /* 5551 and 1555 UINT formats fail on Gfx8/Carrizo´. */
+         if (info->family == CHIP_CARRIZO &&
+             desc->channel[1].size == 5 &&
+             desc->channel[2].size == 5 &&
+             desc->channel[first_non_void].type == UTIL_FORMAT_TYPE_UNSIGNED &&
+             desc->channel[first_non_void].pure_integer)
+            return ~0;
+
+         if (desc->channel[0].size == 5 && desc->channel[1].size == 5 &&
+             desc->channel[2].size == 5 && desc->channel[3].size == 1) {
+            return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
+         }
+         if (desc->channel[0].size == 1 && desc->channel[1].size == 5 &&
+             desc->channel[2].size == 5 && desc->channel[3].size == 5) {
+            return V_008F14_IMG_DATA_FORMAT_5_5_5_1;
+         }
+         if (desc->channel[0].size == 10 && desc->channel[1].size == 10 &&
+             desc->channel[2].size == 10 && desc->channel[3].size == 2) {
+            return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
+         }
+         return ~0;
+      }
+      return ~0;
+   }
+
+   /* uniform formats */
+   switch (desc->channel[first_non_void].size) {
+   case 4:
+      switch (desc->nr_channels) {
+      case 4:
+         /* 4444 UINT formats fail on Gfx8/Carrizo´. */
+         if (info->family == CHIP_CARRIZO &&
+             desc->channel[first_non_void].type == UTIL_FORMAT_TYPE_UNSIGNED &&
+             desc->channel[first_non_void].pure_integer)
+            return ~0;
+
+         return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
+      }
+      break;
+   case 8:
+      switch (desc->nr_channels) {
+      case 1:
+         return V_008F14_IMG_DATA_FORMAT_8;
+      case 2:
+         return V_008F14_IMG_DATA_FORMAT_8_8;
+      case 4:
+         return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
+      }
+      break;
+   case 16:
+      switch (desc->nr_channels) {
+      case 1:
+         return V_008F14_IMG_DATA_FORMAT_16;
+      case 2:
+         return V_008F14_IMG_DATA_FORMAT_16_16;
+      case 4:
+         return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
+      }
+      break;
+   case 32:
+      switch (desc->nr_channels) {
+      case 1:
+         return V_008F14_IMG_DATA_FORMAT_32;
+      case 2:
+         return V_008F14_IMG_DATA_FORMAT_32_32;
+      /* Not supported for render targets */
+      case 3:
+         return V_008F14_IMG_DATA_FORMAT_32_32_32;
+      case 4:
+         return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
+      }
+      break;
+   case 64:
+      if (desc->channel[0].type != UTIL_FORMAT_TYPE_FLOAT && desc->nr_channels == 1)
+         return V_008F14_IMG_DATA_FORMAT_32_32;
+      break;
+   }
+
+   return ~0;
+}
+
 unsigned
 ac_get_cb_format(enum amd_gfx_level gfx_level, enum pipe_format format)
 {

src/amd/common/ac_formats.h

@@ -28,6 +28,11 @@ uint32_t
 ac_translate_tex_numformat(const struct util_format_description *desc,
                            int first_non_void);
 
+uint32_t
+ac_translate_tex_dataformat(const struct radeon_info *info,
+                            const struct util_format_description *desc,
+                            int first_non_void);
+
 unsigned
 ac_get_cb_format(enum amd_gfx_level gfx_level, enum pipe_format format);
 

src/amd/common/ac_gpu_info.c

@@ -895,6 +895,8 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
       case FAMILY_GFX1103:
          identify_chip(GFX1103_R1);
          identify_chip(GFX1103_R2);
+         identify_chip2(GFX1103_R1X, GFX1103_R1);
+         identify_chip2(GFX1103_R2X, GFX1103_R2);
          break;
       case FAMILY_GFX1150:
          identify_chip(GFX1150);
@@ -1221,6 +1223,9 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
    info->has_dcc_constant_encode =
       info->family == CHIP_RAVEN2 || info->family == CHIP_RENOIR || info->gfx_level >= GFX10;
 
+   info->has_etc_support = info->family == CHIP_STONEY || info->family == CHIP_VEGA10 ||
+                           info->family == CHIP_RAVEN || info->family == CHIP_RAVEN2;
+
    info->has_rbplus = info->family == CHIP_STONEY || info->gfx_level >= GFX9;
 
    /* Some chips have RB+ registers, but don't support RB+. Those must

src/amd/common/ac_gpu_info.h

@@ -85,6 +85,7 @@ struct radeon_info {
    bool has_clear_state;
    bool has_distributed_tess;
    bool has_dcc_constant_encode;
+   bool has_etc_support;
    bool has_rbplus;     /* if RB+ registers exist */
    bool rbplus_allowed; /* if RB+ is allowed */
    bool has_load_ctx_reg_pkt;

src/amd/common/ac_shader_args.h

@@ -181,9 +181,9 @@ struct ac_shader_args {
    struct {
       struct ac_arg uniform_shader_addr;
       struct ac_arg sbt_descriptors;
-      struct ac_arg launch_size;
+      struct ac_arg launch_sizes[3];
       struct ac_arg launch_size_addr;
-      struct ac_arg launch_id;
+      struct ac_arg launch_ids[3];
       struct ac_arg dynamic_callable_stack_base;
       struct ac_arg traversal_shader_addr;
       struct ac_arg shader_addr;