Commits on Source (36)
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Caio Oliveira authored
Compiler can't know that array_size() of the offsets parameter in textureGatherOffsets is (at most) 4, so use a MIN2() to make the limit visible. Just adding an assert() gets ignored in Release builds. This fixes the following warning in Release compilation: ``` ../src/compiler/glsl/glsl_to_nir.cpp: In member function ‘virtual void {anonymous}::nir_visitor::visit(ir_texture*)’: ../src/compiler/glsl/glsl_to_nir.cpp:2453:41: warning: writing 1 byte into a region of size 0 [-Wstringop-overflow=] 2453 | instr->tg4_offsets[i][j] = val; | ~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~ In file included from ../src/compiler/glsl/glsl_to_nir.h:31, from ../src/compiler/glsl/glsl_to_nir.cpp:29: ../src/compiler/nir/nir.h:2470:11: note: at offset 8 into destination object ‘nir_tex_instr::tg4_offsets’ of size 8 2470 | int8_t tg4_offsets[4][2]; | ^~~~~~~~~~~ ../src/compiler/glsl/glsl_to_nir.cpp:2453:41: warning: writing 1 byte into a region of size 0 [-Wstringop-overflow=] 2453 | instr->tg4_offsets[i][j] = val; | ~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~ ../src/compiler/nir/nir.h:2470:11: note: at offset 9 into destination object ‘nir_tex_instr::tg4_offsets’ of size 8 2470 | int8_t tg4_offsets[4][2]; | ^~~~~~~~~~~ ``` This is from: `gcc (GCC) 14.1.1 20240522 (Red Hat 14.1.1-4)`. Reviewed-by:Jordan Justen <jordan.l.justen@intel.com> Part-of: <mesa/mesa!29508>
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Rémi Bernon authoredTo avoid a warning with clang when the function is cast to stdcall function pointer on Windows. Part-of: <!29856>
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Alyssa Rosenzweig authoredsee next test. Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <!29861>
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Alyssa Rosenzweig authored
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Alyssa Rosenzweig authored
this is simpler/more correct. Signed-off-by:
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Same hack used by intel_clc. Signed-off-by:
Asahi Lina <lina@asahilina.net> Part-of: <!29861>
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This will prevent the dynamic loader to pick the wrong function once we rename things to the proper API names. In any case, this should have been done all along anyway. Cc: mesa-stable Part-of: <!29855>
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Reviewed-by:
Adam Jackson <ajax@redhat.com> Part-of: <!29855>
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Caio Oliveira authored
These were only being shown before as part of disassemble. Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <!29738>
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The last VGT shader is the mesh shader. Signed-off-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <!29830>
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To avoid duplicating the base user SGPR. Signed-off-by:
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This path is never used by mesh shaders. Signed-off-by:
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It's always 0 for direct draws. Signed-off-by:
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piglit@cf8daaf5...fdf3fc09 Part-of: <!29684>
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This wasn't needed in practice because DGC NV is only enabled for vkd3d-proton and it always uses the global BO list but better to add it anyways. Signed-off-by:
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DGC IBs are considered external IBs because they aren't managed by the winsys and the BO itself isn't really useful. Passing a VA instead will help for future work. Signed-off-by:
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This will disable cases with 2D array views (which could be views to 3D texture) but enables on regular 2D surfaces which seems to work fine. Fixes: 70382f7f ("intel/isl/xe2: Enable route of Sampler LD message to LSC") Signed-off-by:
Tapani Pälli <tapani.palli@intel.com> Reviewed-by:
José Roberto de Souza <jose.souza@intel.com> Part-of: <!29760>
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Some applications may benefit from this while some can get a performance hit. Default to false and make it possible to toggle only for selected workloads. See workaround 14022483228 for some measurements. Signed-off-by:
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I got the image alignment requirements for CPCB surfaces from Bspec authors. The vertical alignment value of 8 was confirmed through the Vulkan CTS test group, dEQP-VK.fragment_shading_rate*layered*. It also happens to match the QPitch alignment requirement documented in the Bspec. Hopefully the CTS will add tests for LOD2+ in order to exercise the horizontal alignment value. With this in place, we can start using Tile4. Closes: #10784 Reviewed-by:
Rohan Garg <rohan.garg@intel.com> Part-of: <!29355>
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No Turnip or ir3 changes required, this was implemented in NIR by Intel. Passes dEQP-VK.spirv_assembly.instruction.*.float_controls2.* Signed-off-by:
Valentine Burley <valentine.burley@gmail.com> Part-of: <!29866>
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Otherwise the assert in si_set_shader_buffer could trigger for blits through clear_buffer on user resources. Reviewed-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <!29867>
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this probably needs better tuning by experts, but it massively improves perf in a number of cases Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <!29842>
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Export functions for GL_OES_vertex_array_object through GetProcAddress on gles1. Signed-off-by:
Zack Middleton <zack@cloemail.com> Reviewed-by:
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InternalBufferSubDataCopyMESA is required for PIPE_CAP_ALLOW_GLTHREAD_BUFFER_SUBDATA_OPT. Signed-off-by:
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The Vulkan spec splits sparse resources in two different features: sparse binding and sparse residency. Sparse binding is much simpler. It requires the resources to be fully bound before being used and it treats them as a black box. We're required to support sparse binding for all the formats that are supported by non-sparse, but that's easy beacause this feature is simpler. Now sparse residency is the one where we're allowed to partially bind resources, and the one that comes with more complicated features such as block shapes and non-opaque binding of images. This feature is subdivided into: - sparseResidencyBuffer - sparseResidencyImage2D - sparseResidencyImage3D - sparseResidency{2,4,8,16}Samples (which refers to 2D images) Notice that there's no sparseResidencyImage1D. And if you read the specs it's clear that sparse residency is meant for non-1D images. Still, supporting it didn't require any extra effort in Anv so we just did it. That's until we started running GL CTS tests on Zink. There's a CTS test that checks for the standard block shapes. It creates 1D images and expects the block shapes for them to be the standard 2D block shapes. While we could very well just patch anv_sparse_calc_image_format_properties() to return the standard 2D block shapes for 1D images, that's just wrong (block shapes for 1D images are just line segments, not rectangles!) so let's just reject this all until maybe one day Vulkan defines sparseResidencyImage1D and we get GL_ARB_sparse_texture3 to match it, or somebody decides to change the GL CTS test. Testcase: KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase Reviewed-by:Paulo Zanoni <paulo.r.zanoni@intel.com> Part-of: <!29337>
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We have to take the number of samples into account when calculating the tile size. If we don't do this, multi-sampled images may end up falling in the "goto out_everything_is_miptail" case, while in reality multi-sampled images don't even have miptails. Also assert that the value is one of the only two values we expect this to be. This assert would have been useful to catch this issue, since with multi-sampled images we were getting values like 16k or 32k depending on the number of samples. This helps move forward progress in some Zink tests, but does not make them fully pass yet, as those tests are full of sub-cases and this only helps some of them: KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess KHR-GL46.sparse_texture2_tests.SparseTexture2Commitment KHR-GL46.sparse_texture2_tests.SparseTexture2Lookup Fixes: 7ef3d652 ("anv/sparse: enable MSAA for Sparse when applicable") Reviewed-by:
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This calculation was wrong for both compressed formats and multi-sampled images. As a result, we misreported the image as having a single miptail. No Vulkan or GL CTS tests were tripping on this bug. I found this while looking for tile size calculations after fixing a similar bug elsewhere in the code. The calculation should now match what we have in anv_sparse_bind_image_memory(), which is widely tested. Reviewed-by:
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Pass struct isl_tile_info to isl_choose_image_alignment_el() and its subfunctions. We already compute isl_tile_info at isl_surf_init_s(), don't make the subfunctions compute it again, just reuse the results. Other subfunctions of isl_surf_init_s() also take the tile info as an argument instead of recomputing it. v2: Rebase after the gen20 version was added. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (v1) Reviewed-by: Nanley Chery <nanley.g.chery@intel.com> (v2) Signed-off-by:
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I've found myself adding this piece of code to our codebase when debugging some Zink sparse failures recently, so let's upstream it. Reviewed-by:
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Since commit 18d8c3ca we were allocating a little more than what we were actually using (2621440 bytes instead of 2097152, aka 0x280000 instead of 0x200000), and we were not properly marking the BO as internal. No applications should be misbehaving because of this. Fixes: 18d8c3ca ("anv: Add missing ANV_BO_ALLOC_INTERNAL") Reviewed-by:
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The code that tries to create a "pretend block shape" for linear tiling surfaces was necessary back when we were going to support sparse residency (non-opaque binds) for non-standard block shapes (since there was uncertainty about TileYs support). That hasn't been the case since before we merged sparse resources upstream, so remove the code and leave an assertion instead, just in case. Reviewed-by:
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There are 3 different places in our code where we calculate the tile size and until recently the 3 implementations were different and with slight bugs. Unify everything and also change the calculation to use tile_info->phys_extent_B. While doing this we move the isl_surf_get_tile_info() calls from anv_sparse_calc_block_shape() to its callers so we total amount of times we call it doesn't change. v2: Adjust the patch now that tile_info is not part of isl_surf anymore. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (v1) Signed-off-by:
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When I wrote sparse resources support for Anv we didn't have TileYs support so I made non-opaque binds work even for non-standard block shapes, which meant the block size could be either 64k or 4k. Since then we merged TileYs support and changed our sparse resources implementation to treat all the non-standard block shape cases as "everything is the miptail", which means non-opaque binds are not possible. So here we adjust the code to more explicitly represent that. Reviewed-by:
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From LLVM. Signed-off-by:
Rhys Perry <pendingchaos02@gmail.com> Reviewed-by:
Daniel Schürmann <daniel@schuermann.dev> Part-of: <!29839>
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- .gitlab-ci/container/build-piglit.sh 1 addition, 1 deletion.gitlab-ci/container/build-piglit.sh
- .gitlab-ci/image-tags.yml 3 additions, 3 deletions.gitlab-ci/image-tags.yml
- docs/features.txt 1 addition, 0 deletionsdocs/features.txt
- src/amd/ci/radeonsi-raven-fails.txt 0 additions, 3 deletionssrc/amd/ci/radeonsi-raven-fails.txt
- src/amd/compiler/aco_ir.cpp 2 additions, 1 deletionsrc/amd/compiler/aco_ir.cpp
- src/amd/vulkan/radv_cmd_buffer.c 18 additions, 18 deletionssrc/amd/vulkan/radv_cmd_buffer.c
- src/amd/vulkan/radv_radeon_winsys.h 2 additions, 2 deletionssrc/amd/vulkan/radv_radeon_winsys.h
- src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c 20 additions, 24 deletionssrc/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
- src/asahi/clc/meson.build 4 additions, 1 deletionsrc/asahi/clc/meson.build
- src/asahi/compiler/agx_compile.h 1 addition, 0 deletionssrc/asahi/compiler/agx_compile.h
- src/asahi/compiler/agx_nir_lower_discard_zs_emit.c 2 additions, 5 deletionssrc/asahi/compiler/agx_nir_lower_discard_zs_emit.c
- src/asahi/compiler/agx_optimizer.c 3 additions, 0 deletionssrc/asahi/compiler/agx_optimizer.c
- src/asahi/compiler/test/test-optimizer.cpp 27 additions, 0 deletionssrc/asahi/compiler/test/test-optimizer.cpp
- src/compiler/glsl/glsl_to_nir.cpp 2 additions, 1 deletionsrc/compiler/glsl/glsl_to_nir.cpp
- src/freedreno/vulkan/tu_device.cc 4 additions, 0 deletionssrc/freedreno/vulkan/tu_device.cc
- src/gallium/drivers/iris/driinfo_iris.h 1 addition, 0 deletionssrc/gallium/drivers/iris/driinfo_iris.h
- src/gallium/drivers/iris/iris_screen.c 3 additions, 0 deletionssrc/gallium/drivers/iris/iris_screen.c
- src/gallium/drivers/radeonsi/si_buffer.c 1 addition, 0 deletionssrc/gallium/drivers/radeonsi/si_buffer.c
- src/gallium/drivers/radeonsi/si_get.c 31 additions, 1 deletionsrc/gallium/drivers/radeonsi/si_get.c
- src/gallium/drivers/virgl/ci/virpipe-gl-fails.txt 0 additions, 7 deletionssrc/gallium/drivers/virgl/ci/virpipe-gl-fails.txt