Draft: intel/isl: Enable Tile4 for CPB surfaces
What does this MR do and why?
intel/isl: Enable Tile4 for CPB surfaces
Requires satisfying the Bspec QPitch restriction of 8 rows. This was
confirmed through the Vulkan CTS test group,
dEQP-VK.fragment_shading_rate*layered*. Thanks to Rohan Garg for
pointing out the restriction.
According to HSD 14013929783, 32 should work if we wanted to use that
instead. We don't follow HSD 14013929783 for now because it seems to
rely on a bit of text that neither that HSD nor our driver is
acknowledging when it shows up the depth/stencil packets. The text is:
QPitch is multiple of tile height (1 << Cv) and should be equal or
greater H computed above.
More evidence for ignoring this text can be found through comparing
revision r114962 vs. revision r112560 of Bspec 6500
(Instruction_3DSTATE_DEPTH_BUFFER) and from reading Bspec 19587
(2D/CUBE Alignment Requirement). From these pages, it can be seen that
the text is part of the block of text focused on Ys/Yf/64 tiling. For
those tilings, we already align the QPitch to the tile height.
By looking into code associated with that HSD, it seems like there are
no special horizontal or vertical image alignments for CPB surfaces. The
Bspec doesn't list any. If and when the Vulkan CTS gets tests for
mipmapped FSR, we'll get more data on this.
Edited by Nanley Chery