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  1. Mar 27, 2020
    • Ville Syrjälä's avatar
      drm/i915: Perform single buffer plane register updates from vblank worker · 9900eb23
      Ville Syrjälä authored and Lyude Paul's avatar Lyude Paul committed
      
      Like we did for pipe gamma let's move the single buffered plane
      register updates to occur from a vblank work.
      
      As the vblank works are a bit on the expensive side (with the qos and
      everything) let's try to do this only when we absolutely have to. If
      we know that the registers we're about to update don't have any
      effect on the old frame we can just directly write the registers
      while the old frame is still being scanned out.
      
      Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      9900eb23
    • Ville Syrjälä's avatar
      drm/i915: Use vblank workers for gamma updates · 4d475a98
      Ville Syrjälä authored and Lyude Paul's avatar Lyude Paul committed
      
      The pipe gamma registers are single buffered so they should only
      be updated during the vblank to avoid screen tearing. In fact they
      really should only be updated between start of vblank and frame
      start because that is the only time the pipe is guaranteed to be
      empty. Already at frame start the pipe begins to fill up with
      data for the next frame.
      
      Unfortunately frame start happens ~1-4 scanlines after the start
      of vblank which in practie doesn't always leave us enough time to
      finish the gamma update in time (gamma LUTs can be several KiB of
      data we have to bash into the registers). However we must try our
      best and so we'll add a vblank work for each pipe from where we
      can do the gamma update.
      
      Even though the vblank worker is running on a high prority thread
      we still have to contend with C-states. If the CPU happens be in
      a deep C-state when the vblank interrupt arrives even the irq
      handler gets delayed massively (I've observed dozens of scanlines
      worth of latency). To avoid that problem we'll use the qos mechanism
      to keep the CPU awake while the vblank work is scheduled.
      
      With all this hooked up we can finally to almost atomic gamma
      updates. It even works across several pipes from the same atomic
      commit which previously was a total fail because we did the
      gamma updates for each pipe serially. In practice we still miss
      the frame start easily and so ~100 pixels of the new frame
      generally make it through with the old gamma. I don't see any
      way to avoid that so we'll just have to live with it. Also it's
      possible that high system load etc. could still cause us blow
      past the end of vblank, but not much we can do there either
      except rewrite the scheduler.
      
      In the future the DSB should take over this responsibility
      which will hopefully avoid some of these issues.
      
      v2: Add missing intel_atomic_state fwd declaration
      v3: Clean up properly when not scheduling the worker
      
      Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      4d475a98
    • Ville Syrjälä's avatar
      drm/i915: Allocate state checker crtc state · 72d0b1cf
      Ville Syrjälä authored and Lyude Paul's avatar Lyude Paul committed
      
      Don't clobber the old state with the results of the hardware readout.
      
      In particualr this clobbers old_crtc_state->commit which caused
      explosions once I hooked up vblank works. Not sure why this doesn't
      cause problems already?
      
      Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      72d0b1cf
    • Ville Syrjälä's avatar
      drm/i915: Move put_domains into crtc_state · d11816aa
      Ville Syrjälä authored and Lyude Paul's avatar Lyude Paul committed
      
      We'll need to defer the power domains put so collect the put_domains
      in the crtc state.
      
      Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      d11816aa
    • Ville Syrjälä's avatar
      drm/i915: Add vblank irq tracepoint · e6badb21
      Ville Syrjälä authored and Lyude Paul's avatar Lyude Paul committed
      
      Add a tracepoint for when we handle the vblank irq.
      
      Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      e6badb21
    • Ville Syrjälä's avatar
      drm/i915: Add LUT load start/end tracepoints · cd1cfee9
      Ville Syrjälä authored and Lyude Paul's avatar Lyude Paul committed
      
      Add tracepoints around the LUT load to allow us to measure how long
      this stuff takes.
      
      Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      cd1cfee9
    • Ville Syrjälä's avatar
      drm/i915: CLRC only affects YUV · be5906d8
      Ville Syrjälä authored and Lyude Paul's avatar Lyude Paul committed
      
      Don't poke at the sprite color correction registers on VLV/CHV when
      scanning out RGB. Turns out RGB data bypasses the color correction
      unit (as it does the CSC and gamma units as well).
      
      Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      be5906d8
    • Ville Syrjälä's avatar
      drm/i915: Optimize chv cgm csc and mode load · 908188b2
      Ville Syrjälä authored and Lyude Paul's avatar Lyude Paul committed
      
      Use I915_WRITE_FW() to blast the CHV cgm csc registers. This needs to
      fast since we have to get it done during the vblank.
      
      Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      908188b2
    • Ville Syrjälä's avatar
      drm/i915: Optimize lut loads · a746437f
      Ville Syrjälä authored and Lyude Paul's avatar Lyude Paul committed
      
      Use I915_WRITE_FW() to write the LUT. It's a ton of registers and all
      the lockdep/etc. overhead adds up.
      
      Probably should ponder about a per-crtc lock for this, or figure
      out if we can just omit the lock entirely...
      
      Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      a746437f
    • Ville Syrjälä's avatar
      drm/i915: Bump frame start delay to max · 6a078142
      Ville Syrjälä authored and Lyude Paul's avatar Lyude Paul committed
      
      The only time we can safely update single buffered registers
      (such as plane/pipe gamma, plane color correction) is between
      start of vblank and frame start. At frame start the pipe will
      already start to process the pixels for the subsequent frame
      and so any register update after that point is likely to cause
      visible artifacts.
      
      Currently we have configured the frame start delay to its minimum
      value (~1 scanline). Bump it to the max (~4 scanlines) to give us
      a bit more time to update those registers without causing visible
      artifacts.
      
      Unfortunately the gamma LUTs can be rather huge so this is still
      not enough time in many so probably not worth the hassle. Also
      frame start delay is generally tagged as "test mode" in the spec
      so not sure we should be extending it at all.
      
      Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      6a078142
    • Ville Syrjälä's avatar
      drm/i915: Use "new" instead of "oldnew" iterrator when appropriate · 68d366d8
      Ville Syrjälä authored and Lyude Paul's avatar Lyude Paul committed
      
      We don't need the old crtc state in some loops which use
      for_each_oldnew_intel_crtc_in_state(). Switch over to
      for_each_new_intel_crtc_in_state() instead.
      
      Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      68d366d8
    • Ville Syrjälä's avatar
      drm/vblank: Add vblank works · f57886ae
      Ville Syrjälä authored and Lyude Paul's avatar Lyude Paul committed
      
      Add some kind of vblank workers. The interface is similar to regular
      delayed works, and also allows for re-scheduling.
      
      Whatever hardware programming we do in the work must be fast
      (must at least complete during the vblank, sometimes during
      the first few scanlines of vblank), so we'll fire up a per-crtc
      high priority thread for this.
      
      [based off patches from Ville Syrjälä <ville.syrjala@linux.intel.com>,
      change below to signoff later]
      
      Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
      Signed-off-by: Lyude Paul's avatarLyude Paul <lyude@redhat.com>
      f57886ae
  2. Mar 25, 2020
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