- Nov 12, 2021
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Tidy up a bit the tree, by prefixing all include/dt-bindings/clock/ files related to Ingenic SoCs with 'ingenic,'. Signed-off-by:
Paul Cercueil <paul@crapouillou.net> Acked-by:
Rob Herring <robh@kernel.org> Acked-by:
Stephen Boyd <sboyd@kernel.org> Signed-off-by:
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- Oct 27, 2021
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Roderick Colenbrander authored
Player LEDs are commonly found on game controllers from Nintendo and Sony to indicate a player ID across a number of LEDs. For example, "Player 2" might be indicated as "-x--" on a device with 4 LEDs where "x" means on. This patch introduces LED_FUNCTION_PLAYER1-5 defines to properly indicate player LEDs from the kernel. Until now there was no good standard, which resulted in inconsistent behavior across xpad, hid-sony, hid-wiimote and other drivers. Moving forward new drivers should use LED_FUNCTION_PLAYERx. Note: management of Player IDs is left to user space, though a kernel driver may pick a default value. Signed-off-by:
Roderick Colenbrander <roderick.colenbrander@sony.com> Acked-by:
Pavel Machek <pavel@ucw.cz> Signed-off-by:
Jiri Kosina <jkosina@suse.cz>
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This rewrites the ux500/u8500 clock bindings in YAML schema and extends them with the PRCC reset controller. The bindings are a bit idiomatic but it just reflects their age, the ux500 platform was used as guinea pig for early device tree conversion of platforms in 2015. The new subnode for the reset controller follows the pattern of the old bindings and adds a node with reset-cells for this. Cc: devicetree@vger.kernel.org Cc: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by:
Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20210921184803.1757916-1-linus.walleij@linaro.org Signed-off-by:
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- Oct 26, 2021
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Srinivas Kandagatla authored
move all LPASS audio ports defines from q6afe.h to q6dsp-lpass-ports.h as these belong to LPASS IP. Also this move helps in reusing this header across multiple audio frameworks on Qualcomm Audio DSP. This patch is split out of the dt-bindings patch to enable easy review. Signed-off-by:
Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Acked-by:
Mark Brown <broonie@kernel.org>
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Add clock IDs for derived and received reference clock output. Signed-off-by:
Swapnil Jakhade <sjakhade@cadence.com> Acked-by:
Vinod Koul <vkoul@kernel.org>
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- Oct 25, 2021
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Srinivasa Rao Mandadapu authored
Add header defining for lpass internal digital codecs rx,tx and va dai node id's. Signed-off-by:
Srinivasa Rao Mandadapu <srivasam@codeaurora.org> Link: https://lore.kernel.org/r/1633670491-27432-1-git-send-email-srivasam@codeaurora.org Signed-off-by:
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- Oct 20, 2021
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Miquel Raynal authored
Declare ADC1 clkctrl which feeds the magnetic-reader/ADC1 hardware module. Signed-off-by:
Miquel Raynal <miquel.raynal@bootlin.com> Acked-by:
Tony Lindgren <tony@atomide.com> Signed-off-by:
Lee Jones <lee.jones@linaro.org> Link: https://lore.kernel.org/r/20211015081506.933180-2-miquel.raynal@bootlin.com
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- Oct 13, 2021
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The camera clock controller clock provider have a bunch of generic properties that are needed in a device tree. Add the CAMCC clock IDs for camera client to request for the clocks. Signed-off-by:
Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1633567425-11953-1-git-send-email-tdas@codeaurora.org Signed-off-by:
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The LPASS(Low Power Audio Subsystem) clock provider have a bunch of generic properties that are needed in a device tree. Add the LPASS clock IDs for LPASS PIL client to request for the clocks. Signed-off-by:
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This will be required to support the modem. Signed-off-by:
Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210923162645.23257-7-konrad.dybcio@somainline.org Signed-off-by:
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This should be the last "add missing clocks" commit, as to my knowledge there are no more clocks registered within gcc. Signed-off-by:
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Add necessary NoC clocks to provide frequency sources for relevant branch clocks. Signed-off-by:
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Add support for RPM-managed clocks on the QCM2290 platform. Signed-off-by:
Shawn Guo <shawn.guo@linaro.org> Link: https://lore.kernel.org/r/20210917030434.19859-4-shawn.guo@linaro.org Reviewed-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by:
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Add Global Clock Controller (GCC) driver for QCM2290. This is a porting of gcc-scuba driver from CAF msm-4.19, with GDSC support added on top. Because the alpha_pll on the platform has a different register layout (offsets), its own clk_alpha_pll_regs_offset[] is used in the driver. Signed-off-by:
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- Oct 09, 2021
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Sam Protsenko authored
Clock controller driver is designed to have separate instances for each particular CMU. So clock IDs in this bindings header also start from 1 for each CMU. Signed-off-by:
Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Acked-by:
Sylwester Nawrocki <s.nawrocki@samsung.com>
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- Oct 08, 2021
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Enric Balletbo i Serra authored
Reset the DSI hardware is needed to prevent different settings between the bootloader and the kernel. While here, also remove the undocumented and also not used 'mediatek,syscon-dsi' property. Signed-off-by:
Enric Balletbo i Serra <enric.balletbo@collabora.com> Acked-by:
Matthias Brugger <matthias.bgg@gmail.com>
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Enric Balletbo i Serra authored
Reset the DSI hardware is needed to prevent different settings between the bootloader and the kernel. Signed-off-by:
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Enric Balletbo i Serra authored
The DT binding includes for reset controllers are located in include/dt-bindings/reset/. Move the Mediatek reset constants in there. Signed-off-by:
Guenter Roeck <linux@roeck-us.net> Reviewed-by:
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- Oct 05, 2021
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Lucas Stach authored
This adds the defines for the power domains provided by the DISP blk-ctrl. Signed-off-by:
Lucas Stach <l.stach@pengutronix.de> Acked-by:
Shawn Guo <shawnguo@kernel.org>
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Lucas Stach authored
This adds the defines for the power domains provided by the VPU blk-ctrl. Signed-off-by:
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- Oct 02, 2021
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This patch adds rsel define for mt8195. Signed-off-by:
Zhiyong Tao <zhiyong.tao@mediatek.com> Acked-by:
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- Sep 30, 2021
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Jacky Bai authored
Add the clock dt-binding file for i.MX8ULP. For pcc node, it will also be used as a reset controller, so add the '#reset-cells' property description and add the pcc reset IDs. Signed-off-by:
Jacky Bai <ping.bai@nxp.com> Reviewed-by:
Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20210914065208.3582128-2-ping.bai@nxp.com Signed-off-by:
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- Sep 28, 2021
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Srinivas Kandagatla authored
Qualcomm Generic Packet router aka GPR is the IPC mechanism found in AudioReach next generation signal processing framework to perform command and response messages between various processors. GPR has concepts of static and dynamic port, all static services like APM (Audio Processing Manager), PRM (Proxy resource manager) have fixed port numbers where as dynamic services like graphs have dynamic port numbers which are allocated at runtime. All GPR packet messages will have source and destination domain and port along with opcode and payload. This support is added using existing APR driver to reuse most of the code. Signed-off-by:
Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Signed-off-by:
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- Sep 27, 2021
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Sibi Sankar authored
Delete unused power-domain definitions exposed by AOSS QMP. Signed-off-by:
Sibi Sankar <sibis@codeaurora.org> Reviewed-by:
Stephen Boyd <swboyd@chromium.org> Acked-by:
Matthias Kaehlcke <mka@chromium.org> Signed-off-by:
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- Sep 23, 2021
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Martin Blumenstingl authored
Setting the video clocks requires fine-tuned adjustments of various video clocks. Export the required ones to allow changing the video clock for the CVBS and HDMI outputs at runtime. Signed-off-by:
Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by:
Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20210713232510.3057750-7-martin.blumenstingl@googlemail.com
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- Sep 21, 2021
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Konrad Dybcio authored
Add compatible and constants for the power domains exposed by the RPMH in the Qualcomm SM6350 platform. Acked-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by:
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Vladimir Lypak authored
Add compatible and constants for the power domains exposed by the RPM in the Qualcomm MSM8953 platform. Signed-off-by:
Vladimir Lypak <vladimir.lypak@gmail.com> Signed-off-by:
Adam Skladowski <a_skl39@protonmail.com> Signed-off-by:
Sireesh Kodali <sireeshkodali1@gmail.com> Acked-by:
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- Sep 14, 2021
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Add MT8195 clock dt-bindings, includes topckgen, apmixedsys, infracfg_ao, pericfg_ao and subsystem clocks. Signed-off-by:
Chun-Jie Chen <chun-jie.chen@mediatek.com> Acked-by:
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- Sep 13, 2021
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Srinivasa Rao Mandadapu authored
Add header defining for lpass internal digital codecs rx,tx and va dai node id's. Signed-off-by:
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- Sep 01, 2021
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jason-jh.lin authored
Add gce header file to define the gce subsys id, hardware event id and constant for mt8195. Signed-off-by:
jason-jh.lin <jason-jh.lin@mediatek.com> Signed-off-by:
Jassi Brar <jaswinder.singh@linaro.org>
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- Aug 30, 2021
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Yongqiang Niu authored
Add documentation for the mt8192 gce. Add gce header file defined the gce hardware event, subsys number and constant for mt8192. Signed-off-by:
Yongqiang Niu <yongqiang.niu@mediatek.com> Reviewed-by:
Hsin-Yi Wang <hsinyi@chromium.org> Signed-off-by:
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- Aug 29, 2021
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Add device tree bindings for global clock controller on SM6350 SoC. Signed-off-by:
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Add support for RPMH clocks on SM6350 SoCs. Reviewed-by:
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Add device tree bindings for global clock controller on SM6115 and SM4250 SoCs (pin and software compatible). Signed-off-by:
Iskren Chernev <iskren.chernev@gmail.com> Link: https://lore.kernel.org/r/20210805161107.1194521-2-iskren.chernev@gmail.com Reviewed-by:
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- Aug 26, 2021
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Add a driver for managing MultiMedia SubSystem clocks on msm8994 and its derivatives. Signed-off-by:
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Add bindings and compatible to document MSM8953 GCC (Global Clock Controller) driver. Signed-off-by:
Vladimir Lypak <junak.pub@gmail.com> Signed-off-by:
Sireesh Kodali <sireeshkodali@protonmail.com> Link: https://lore.kernel.org/r/Q6uB3NRxqtD8Prsmliv8ZdsTXGeviv7lb2jQ743jr1E@cp4-web-036.plabs.ch Reviewed-by:
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- Aug 24, 2021
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Marek Vasut authored
Add missing M7 core clock entry to the iMX8MN clock driver. Signed-off-by:
Marek Vasut <marex@denx.de> Reviewed-by:
Fabio Estevam <festevam@gmail.com> Cc: Abel Vesa <abel.vesa@nxp.com> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Shawn Guo <shawnguo@kernel.org> Link: https://lore.kernel.org/r/20210819202036.2084782-1-marex@denx.de Signed-off-by:
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- Aug 23, 2021
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The zte zx platform had been removed in commit 89d4f98a ("ARM: remove zte zx platform"), so this header is no longer needed. Cc: Arnd Bergmann <arnd@arndb.de> Cc: Jun Nie <jun.nie@linaro.org> Cc: Shawn Guo <shawnguo@kernel.org> Signed-off-by:
Zenghui Yu <yuzenghui@huawei.com> Link: https://lore.kernel.org/r/20210821030924.192-2-yuzenghui@huawei.com Signed-off-by:
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The zx296718-clkc driver had been removed in commit bcbe6005 ("clk: remove zte zx driver"), so this header is no longer needed. Cc: Arnd Bergmann <arnd@arndb.de> Cc: Jun Nie <jun.nie@linaro.org> Cc: Shawn Guo <shawnguo@kernel.org> Signed-off-by:
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- Aug 22, 2021
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Christine Zhu authored
Add toprgu reset-controller header file for MT8195 platform. Signed-off-by:
Christine Zhu <Christine.Zhu@mediatek.com> Acked-by:
Wim Van Sebroeck <wim@linux-watchdog.org>
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