<7> [613.032847] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling PW_2
<7> [613.033176] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling dpio-common-b
<7> [613.035909] i915 0000:00:02.0: [drm:intel_cdclk_dump_config [i915]] Changing CDCLK to 316800 kHz, VCO 633600 kHz, ref 19200 kHz, bypass 19200 kHz, voltage level 13
<7> [613.036476] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:142:DDI B/PHY B]
<7> [613.036732] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:152:DDI C/PHY C]
<7> [613.038380] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.36 [i915]] PORT PLL A
<7> [613.038911] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.36 [i915]] PORT PLL B
<7> [613.039293] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.36 [i915]] PORT PLL C
<7> [613.039576] i915 0000:00:02.0: [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 0x2, on? 0) for [CRTC:104:pipe B]
<7> [613.041219] i915 0000:00:02.0: [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
<7> [613.042076] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling DDI_IO_B
<7> [613.042449] i915 0000:00:02.0: [drm:intel_enable_transcoder [i915]] enabling pipe B
<7> [613.044699] i915 0000:00:02.0: [drm:intel_audio_codec_enable [i915]] [CONNECTOR:143:HDMI-A-1][ENCODER:142:DDI B/PHY B] Enable audio codec on pipe B, 32 bytes ELD
<7> [613.045051] i915 0000:00:02.0: [drm:audio_config_hdmi_pixel_clock [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
<7> [613.046328] i915 0000:00:02.0: [drm:hsw_audio_config_update [i915]] using automatic N
<7> [613.061781] i915 0000:00:02.0: [drm:verify_connector_state [i915]] [CONNECTOR:143:HDMI-A-1]
<7> [613.062150] i915 0000:00:02.0: [drm:intel_modeset_verify_crtc [i915]] [CRTC:104:pipe B]
<7> [613.062685] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.36 [i915]] PORT PLL B
<7> [613.069763] [drm:drm_mode_setcrtc] [CRTC:141:pipe C]
<7> [613.112294] i915 0000:00:02.0: [drm:i915_fifo_underrun_reset_write [i915]] Re-arming FIFO underruns on pipe B
<7> [613.137085] i915 0000:00:02.0: [drm:i915_fifo_underrun_reset_write [i915]] Re-arming FIFO underruns on pipe B
<7> [613.195135] [drm:drm_mode_setcrtc] [CRTC:104:pipe B]
<7> [613.195229] [drm:drm_mode_setcrtc] [CONNECTOR:143:HDMI-A-1]
<7> [613.211977] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:100:cursor B] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm, swm, stwm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7,*twm, swm, stwm
<7> [613.212291] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:100:cursor B] lines 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 4, 4, 4, 2, 2, 2, 2, 2, 0, 0, 0
<7> [613.212502] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:100:cursor B] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 12, 7, 7, 7, 7, 7, 25, 0, 0
<7> [613.212710] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:100:cursor B] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 12, 12, 13, 8, 8, 8, 8, 8, 26, 0, 0
<6> [613.344720] PM: suspend entry (deep)
<6> [613.348722] Filesystems sync: 0.003 seconds