Few tests - dmesg-warn/dmesg-fail - *ERROR* GT workaround lost on application! (reg[9424]=0xfffffffe, relevant bits were 0x2 vs expected 0x0)

https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13401/re-dg2-13/igt@gem_ccs@suspend-resume.html#dmesg-warnings309

<7> [279.940312] i915 0000:03:00.0: [drm:intel_cdclk_dump_config [i915]] Current CDCLK 19200 kHz, VCO 0 kHz, ref 38400 kHz, bypass 19200 kHz, voltage level 0
<7> [279.940404] i915 0000:03:00.0: [drm:intel_cdclk_init_hw [i915]] Sanitizing cdclk programmed by pre-os
<7> [279.940626] i915 0000:03:00.0: [drm:gen9_dbuf_slices_update [i915]] Updating dbuf slices to 0x1
<7> [279.944382] i915 0000:03:00.0: [drm:intel_power_well_enable [i915]] enabling always-on
<7> [279.944606] i915 0000:03:00.0: [drm:intel_power_well_enable [i915]] enabling DC_off
<7> [279.944696] i915 0000:03:00.0: [drm:gen9_set_dc_state.part.0 [i915]] Setting DC state from 00 to 00
<7> [279.944868] i915 0000:03:00.0: [drm:intel_power_well_enable [i915]] enabling PW_2
<7> [279.945031] i915 0000:03:00.0: [drm:intel_power_well_enable [i915]] enabling PW_A
<7> [279.945146] i915 0000:03:00.0: [drm:intel_power_well_enable [i915]] enabling PW_B
<7> [279.945258] i915 0000:03:00.0: [drm:intel_power_well_enable [i915]] enabling PW_C
<7> [279.945367] i915 0000:03:00.0: [drm:intel_power_well_enable [i915]] enabling PW_D
<7> [279.946184] PM: early resume of devices complete after 8.212 msecs
<6> [279.961953] nvme nvme0: 20/0/0 default/read/poll queues
<3> [279.994353] i915 0000:03:00.0: [drm] *ERROR* GT workaround lost on application! (reg[9424]=0xfffffffe, relevant bits were 0x2 vs expected 0x0)
<3> [279.994532] i915 0000:03:00.0: [drm] *ERROR* GT workaround lost on init! (reg[9424]=0xfffffffe, relevant bits were 0x2 vs expected 0x0)
<6> [279.994582] i915 0000:03:00.0: [drm] GT0: GuC firmware i915/dg2_guc_70.bin version 70.8.0
<6> [279.994585] i915 0000:03:00.0: [drm] GT0: HuC firmware i915/dg2_huc_gsc.bin version 7.10.3
<7> [280.011513] i915 0000:03:00.0: [drm:intel_guc_fw_upload [i915]] GT0: GUC: init took 10ms, freq = 2000MHz, before = 2000MHz, status = 0x8002F034, count = 0, ret = 0
<7> [280.012449] i915 0000:03:00.0: [drm:guc_enable_communication [i915]] GT0: GUC: communication enabled
<6> [280.015503] i915 0000:03:00.0: [drm] GT0: GUC: submission enabled
<6> [280.015505] i915 0000:03:00.0: [drm] GT0: GUC: SLPC enabled
<6> [280.016772] i915 0000:03:00.0: [drm] GT0: GUC: RC enabled