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- Mar 11, 2024
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Mauro Carvalho Chehab authored
There are two functions there that aren't unused. Drop the dead code. Acked-by:
Katarzyna Piecielska <katarzyna.piecielska@intel.com> Signed-off-by:
Mauro Carvalho Chehab <mchehab@kernel.org>
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Mauro Carvalho Chehab authored
There were some changes at test_list that caused it to stop working. Fix them. Acked-by:
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Zbigniew Kempczyński authoredFill the gap with testing render-copy for xe driver. Currently only few basic render-copy checks are executing within xe_intel_bb@render. xe_render_copy introduces new checks comparing to gem_render_copy test. During my work on enabling render-copy on LunarLake I've used same r6 subregisters like on previous platforms what causes full render-copy between surfaces worked but partials were not. I decided to include square and v/h stripes tests to verify cofficients for barycentric coordinates matches expected <x,y> position. More stressful is random subtest which randomizes width and height as well as division point (it copies four rectangles to destination surface). Cc: Matthew Auld <matthew.auld@intel.com> Reviewed-by:
Matthew Auld <matthew.auld@intel.com> Link: https://lore.kernel.org/r/20240306150219.301977-5-zbigniew.kempczynski@intel.com Signed-off-by:
Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
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Zbigniew Kempczyński authored
Refactor a bit handling different tilings in render-copy pipeline and add Tile64 which I want to exercise in xe_render_copy test. Cc: Matthew Auld <matthew.auld@intel.com> Acked-by:
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Zbigniew Kempczyński authored
Dumping to png where we want to pass width, height and/or other values is much easier when we use printf style filename formatting instead preparing string with filename separately. Replace current write to raw png from single string to string formatting. Cc: Matthew Auld <matthew.auld@intel.com> Reviewed-by:
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Zbigniew Kempczyński authored
Due to differences between supported tilings on newer hardware (xe) we use for_each_tiling() macro in blitter tests. Assuming these tilings are also valid for render pipeline we need to convert them to legacy tilings (I915_TILING_*). Add helper which does this job allowing to iterate on supported tilings using blitter macros. Cc: Matthew Auld <matthew.auld@intel.com> Reviewed-by:
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Bhanuprakash Modem authoredAs pc8-residency tests are not valid for XE, block these tests to not run on CI. Signed-off-by:
Bhanuprakash Modem <bhanuprakash.modem@intel.com> Reviewed-by:
Jeevan B <jeevan.b@intel.com>
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- Mar 08, 2024
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Rodrigo Vivi authored
After the introduction of kernel commit 23cf006beac3 ("drm/xe: Runtime PM wake on every IOCTL") the many ioctl called during dpms_on_off might be forcing rpm to transition back and forth active to suspend. Then, when setting the d3cold_allowed during a transitional runtime_state, we got some situation where the runtime pm might decide to keep the device awake for a very long time even with runtime_usage == 0. Then our tests would start to break like crazy: (xe_pm:29453) igt_pm-WARNING: timeout: pm_status expected:suspended, got:active (xe_pm:29453) CRITICAL: Test assertion failure function __igt_unique____real_main473, file ../tests/intel/xe_pm.c:556: (xe_pm:29453) CRITICAL: Failed assertion: in_d3(device, d->state) Stack trace: #0 ../lib/igt_core.c:1989 __igt_fail_assert() #1 ../tests/intel/xe_pm.c:432 __igt_unique____real_main473() #2 ../tests/intel/xe_pm.c:473 main() #3 [__libc_start_call_main+0x7a] #4 [__libc_start_main+0x8b] #5 [_start+0x25] Subtest d3hot-basic failed. **** DEBUG **** (xe_pm:29453) igt_pm-WARNING: timeout: pm_status expected:suspended, got:active By simply waiting the suspended state before we touch d3cold_allowed, we get our tests back to a sane state. Cc: Anshuman Gupta <anshuman.gupta@intel.com> Signed-off-by:Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by:
Anshuman Gupta <anshuman.gupta@intel.com>
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Matthew Auld authored
On Xe2 using the L3:XD (wb-transient) caching mode, which is intended for display use, verify we don't observe display corruption when rendering unto the display surface. Transient cache entries should be flushed by the time we do the flip, if not we will detect pipe crc mismatch vs reference fb. Signed-off-by:
Nirmoy Das <nirmoy.das@intel.com>
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Matthew Auld authored
At least on Xe2 it looks like we can just use MOCS index zero to defer the selected caching mode to that of the PAT index. This will be useful in an upcoming patch. v2: (Zbigniew) - Let's go with intel_get_defer_to_pat_mocs_index() Signed-off-by:
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Matthew Auld authored
Allow the caller the set the intel_buf.mocs_index as part of the usual _full variants. Signed-off-by:
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Matthew Auld authored
We want to allow the caller the set any valid MOCS index as part of the the intel_buf. Drop the MOCS enum in favour of raw mocs_index. Also drop the getter/setter interface, for which there are no current callers for the setter part. In the next patch we will expose the raw mocs_index. Should be no functional changes here. v2 (Zbigniew): - Rather just pass along UC directly to lower layers. Signed-off-by:
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Matthew Auld authored
Currently we just default to index=0, but that can have different meaning between HW versions. Rather just default to UC mocs index. Signed-off-by:
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Matthew Auld authored
UC looks to be the sensible default here, since it will work with display engine if rendering onto scanout surface. Use the matching helper. Signed-off-by:
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- Mar 06, 2024
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Bhanuprakash Modem authored
As Driver prefers PSR over DRRS, we can't enable PSR & DRRS together. Hence block PSR + DRRS subtests in CI. Signed-off-by:
Jouni Högander <jouni.hogander@intel.com>
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Bhanuprakash Modem authored
As Driver prefers PSR over DRRS, we can't enable PSR & DRRS together. Hence block PSR + DRRS subtests in CI. Signed-off-by:
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IGT runner is case insensitive, so, for machine, it doesn't matter. Yet, as dictionaries are case sensitive, better to place the tests on a canonical form, e. g. in lower case. Signed-off-by:
Kamil Konieczny <kamil.konieczny@linux.intel.com>
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If there is an error in the register list provided to GuC by the KMD then GuC will refuse to capture the invalid entries. This is reported as a 'partial-capture' when decoding the register state. Check for this and flag it as an error. v2: Keep includes in alphabetical order (review feedback from Kamil). Signed-off-by:
John Harrison <John.C.Harrison@Intel.com> Reviewed-by:
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Vitaly Prosyak authoredCombine the following sub-tests: creation, encoding and destroy as a single sub-test for vce encoder. It is a similar change as commit 40ed7446. v2: Improve commit message (Kamil) Cc: Christian Koenig <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Michael Strawbridge <michael.strawbridge@amd.com> Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com> Cc: Petri Latvala <adrinael@adrinael.net> Signed-off-by:
Michael Strawbridge <michael.strawbridge@amd.com> Signed-off-by:
Vitaly Prosyak <vitaly.prosyak@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
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- Mar 05, 2024
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Let's add a helper that can easily verify that the gt id points to the media gt. Signed-off-by:
Piotr Piórkowski <piotr.piorkowski@intel.com> Acked-by:
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Add functions to read/write 64-bit values from MMIO Signed-off-by:
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Let's add a new macro that will be used to verify whether one value is aligned to the other. Signed-off-by:
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- Mar 04, 2024
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This test was recently updated to not fall foul of a particular workaround. The w/a tag itself was missed, however. So, add that in to make it easier to find in the future. Signed-off-by:
Vinay Belgaumkar <vinay.belgaumkar@intel.com>
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There is a w/a on MTL that prevents concurrent execution of multiple processes on RCS and CCS. The 'spin-all-new' test is explicitly testing such execution across all engines. So either the entire test must be skipped on MTL or just the compute engine must be skipped. Do the latter as that at least leaves some test coverage in place. Signed-off-by:
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Now that we don't need call igt_display_require() twice, remove the duplicate calls, previously needed to expose the writeback output. Signed-off-by:
Arthur Grillo <arthurgrillo@riseup.net> Acked-by:
Pekka Paalanen <pekka.paalanen@collabora.com> Reviewed-by:
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As stated at [1], we first need to set DRM_CLIENT_CAP_ATOMIC before setting DRM_CLIENT_CAP_WRITEBACK_CONNECTORS. Fix that. [1]: https://docs.kernel.org/gpu/drm-uapi.html?highlight=writeback#c.DRM_CLIENT_CAP_WRITEBACK_CONNECTORS Fixes: 3642acbb ("lib/igt_kms: Add writeback support") Signed-off-by:
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Unify documentation for Intel i915 tests that we have by moving common parts to be available for all tests. Signed-off-by:
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Unify documentation for Intel i915 tests that we have by moving common parts to be available for all tests. v2: fix checkpatch warning Signed-off-by:
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Unify documentation for Intel i915 tests that we have by moving common parts to be available for all tests. Signed-off-by:
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Unify documentation for Intel i915 tests that we have by moving common parts to be available for all tests. v2: fix checkpatch warnings Signed-off-by:
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Unify documentation for Intel i915 tests that we have by moving common parts to be available for all tests. v2: rebase on master, add 3 more files with refactoring (tests/intel/api_intel_allocator.c, tests/intel/api_intel_bb.c, tests/intel/gem_busy.c) Signed-off-by:
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Juha-Pekka Heikkilä authored
On Xe device legacy blitter size rules don't need to be applied Signed-off-by:
Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Reviewed-by:
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The new MAXMIN test will oscillate between the max and min refresh rates every frame to stress test the panel. This is useful for manual profiling of flicker. v2: - Added to the set v3: (Bhanu) - Rebase - Add testplan documentation v4: (Bhanu) - Don't execute other stuff in max-min v5: (Bhanu) - Adjust Pass/Fail criteria - Tweak min rate for Intel h/w Signed-off-by:
Sean Paul <seanpaul@chromium.org> Reviewed-by:
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Instead of passing just one rate into flip_and_measure, pass in an array to allow for tests which vary the refresh rate from one frame to the next. Currently the test will just cycle through the rates in order per frame. Just framework, no changes to any tests. v2: - Added to the set v3: (Bhanu) - Rebase v4: (Bhanu) - Fix refresh rate selection Signed-off-by:
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Add a --static-image argument which will paint both framebuffers identically. This allows us to profile VRR flicker on the panel. v2: - Add short opt to the main callsite (Bhanu) v3: (Bhanu) - Rebase - Nit: 's/d:r:s:/drs:/' Cc: Mark Yacoub <markyacoub@chromium.org> Signed-off-by:
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Upgrade the tiny box in the top left corner to some vertical color bars with horizontal grey and white bars at the bottom. v2: - Removed hardcoded bar heights - Made number of vertical bars configurable - Fill in the entire screen horizontally v3: (Bhanu) - Rebase - Drop static variable Cc: Mark Yacoub <markyacoub@chromium.org> Cc: Bhanuprakash Modem <bhanuprakash.modem@intel.com> Signed-off-by:
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Using --duration argument, otherwise use default. v2: - Add short opt to the main callsite (Bhanu) v3: (Bhanu) - Rebase - Nit: 's/d:r:/dr:/' Cc: Mark Yacoub <markyacoub@chromium.org> Reviewed-by:
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Instead of always using the midpoint, introduce optional argument --refresh-rate to allow callers to specify the target refresh rate for the test. v2: - Add short opt to the main callsite (Bhanu) v3: (Bhanu) - Rebase v4: (Bhanu) - Not necessary to keep the refresh rate within the VRR range Cc: Mark Yacoub <markyacoub@chromium.org> Reviewed-by:
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vtest_ns is derived from data->range which is fixed. Move it into data_t and generate it once in prepare_test(). v2: (Bhanu) - Rebase Cc: Mark Yacoub <markyacoub@chromium.org> Reviewed-by:
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Consolidate the 2 fb variables into an array. No functional changes. v2: - Clarified commit msg (Bhanu) v3: (Bhanu) - Rebase Cc: Mark Yacoub <markyacoub@chromium.org> Reviewed-by:
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