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commit f4e9894b6952a2819937f363cd42e7cd7894a1e4Author: Chris Wilson <chris@chris-wilson.co.uk>Date: Tue Jan 14 10:56:47 2020 +0000 drm/i915/pmu: Correct the rc6 offset upon enabling The rc6 residency starts ticking from 0 from BIOS POST, but the kernel starts measuring the time from its boot. If we start measuruing I915_PMU_RC6_RESIDENCY while the GT is idle, we start our sampling from 0 and then upon first activity (park/unpark) add in all the rc6 residency since boot. After the first park with the sampler engaged, the sleep/active counters are aligned. v2: With a wakeref to be sure Closes: https://gitlab.freedesktop.org/drm/intel/issues/973 Fixes: df6a42053513 ("drm/i915/pmu: Ensure monotonic rc6") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200114105648.2172026-1-chris@chris-wilson.co.uk
After we fix the sampling, I expect there to be a couple of HW bugs to investigate. On byt/bsw related to the PCU, and on gen6/gen7 related to coarse evaluation intervals for HW rc6.
Note that snb on CI_DRM_7736+ is a new bug. That's the case where HW rc6 is not as fast as soft-rc6 and so while we do enter rc6, it's significantly worse than expected. If we can't find a way to idle faster, we may just have to make the test more lenient -- some rc6 is better than none!