<6> [131.853962] i915 0000:00:02.0: [drm] GT0: GUC: submission enabled
<6> [131.853963] i915 0000:00:02.0: [drm] GT0: GUC: SLPC enabled
<6> [131.859718] Checking 1 whitelisted registers on vcs0 (RING_NONPRIV) [guc]
<7> [131.879932] i915 0000:00:02.0: [drm:intel_guc_context_reset_process_msg [i915]] GT0: GUC: Got context reset notification: 0x1005 on vcs0, exiting = no, banned = no
<6> [131.924279] i915 0000:00:02.0: [drm] GPU HANG: ecode 12:0:00000000
<6> [131.929478] Checking 1 whitelisted registers on vcs0 (RING_NONPRIV) [device]
<5> [131.931873] i915 0000:00:02.0: [drm] GT0: Resetting chip for live_workarounds
<3> [131.931973] i915 0000:00:02.0: [drm] *ERROR* GT0: GUC: Bad context sched_state 0x0, ctx_id 4101
<3> [131.932051] i915 0000:00:02.0: [drm] *ERROR* GT0: GUC: CT: Failed to process request 1002 (-EPROTO)
<3> [131.932053] i915 0000:00:02.0: [drm] *ERROR* GT0: GUC: CT: Failed to process CT message (-EPROTO) 03 00 00 00 02 10 00 90 05 10 00 00 01 00 00 00
<6> [131.933239] i915 0000:00:02.0: [drm] GT0: GuC firmware i915/tgl_guc_70.bin version 70.13.0
<6> [131.933242] i915 0000:00:02.0: [drm] GT0: HuC firmware i915/tgl_huc.bin version 7.9.3
<7> [131.937564] i915 0000:00:02.0: [drm:intel_guc_fw_upload [i915]] GT0: GUC: init took 0ms, freq = 1350MHz, before = 1350MHz, status = 0x8002F0EC, count = 0, ret = 0
<7> [131.939870] i915 0000:00:02.0: [drm:guc_enable_communication [i915]] GT0: GUC: communication enabled
<6> [131.942196] i915 0000:00:02.0: [drm] GT0: HuC: authenticated for all workloads
<6> [131.944600] i915 0000:00:02.0: [drm] GT0: GUC: submission enabled
<6> [131.944601] i915 0000:00:02.0: [drm] GT0: GUC: SLPC enabled
<6> [131.951418] Checking 1 whitelisted registers on vcs1 (RING_NONPRIV) [guc]
<7> [131.971711] i915 0000:00:02.0: [drm:intel_guc_context_reset_process_msg [i915]] GT0: GUC: Got context reset notification: 0x1005 on vcs1, exiting = no, banned = no
<6> [132.008561] i915 0000:00:02.0: [drm] GPU HANG: ecode 12:0:00000000
<6> [132.013755] Checking 1 whitelisted registers on vcs1 (RING_NONPRIV) [device]
<5> [132.016147] i915 0000:00:02.0: [drm] GT0: Resetting chip for live_workarounds
<6> [132.017406] i915 0000:00:02.0: [drm] GT0: GuC firmware i915/tgl_guc_70.bin version 70.13.0
<6> [132.017408] i915 0000:00:02.0: [drm] GT0: HuC firmware i915/tgl_huc.bin version 7.9.3
<7> [132.021843] i915 0000:00:02.0: [drm:intel_guc_fw_upload [i915]] GT0: GUC: init took 0ms, freq = 1350MHz, before = 1350MHz, status = 0x8002F0EC, count = 0, ret = 0
<7> [132.024149] i915 0000:00:02.0: [drm:guc_enable_communication [i915]] GT0: GUC: communication enabled
<6> [132.026473] i915 0000:00:02.0: [drm] GT0: HuC: authenticated for all workloads
<6> [132.033543] i915 0000:00:02.0: [drm] GT0: GUC: submission enabled
<6> [132.033545] i915 0000:00:02.0: [drm] GT0: GUC: SLPC enabled
<6> [132.040314] Checking 1 whitelisted registers on vecs0 (RING_NONPRIV) [guc]
<7> [132.060614] i915 0000:00:02.0: [drm:intel_guc_context_reset_process_msg [i915]] GT0: GUC: Got context reset notification: 0x1005 on vecs0, exiting = no, banned = no
<6> [132.099341] i915 0000:00:02.0: [drm] GPU HANG: ecode 12:0:00000000
<6> [132.104533] Checking 1 whitelisted registers on vecs0 (RING_NONPRIV) [device]
<5> [132.108100] i915 0000:00:02.0: [drm] GT0: Resetting chip for live_workarounds
<6> [132.109374] i915 0000:00:02.0: [drm] GT0: GuC firmware i915/tgl_guc_70.bin version 70.13.0
<6> [132.109378] i915 0000:00:02.0: [drm] GT0: HuC firmware i915/tgl_huc.bin version 7.9.3
<7> [132.113773] i915 0000:00:02.0: [drm:intel_guc_fw_upload [i915]] GT0: GUC: init took 0ms, freq = 1350MHz, before = 1350MHz, status = 0x8002F0EC, count = 0, ret = 0
<7> [132.116080] i915 0000:00:02.0: [drm:guc_enable_communication [i915]] GT0: GUC: communication enabled
<6> [132.118388] i915 0000:00:02.0: [drm] GT0: HuC: authenticated for all workloads
<6> [132.120809] i915 0000:00:02.0: [drm] GT0: GUC: submission enabled
<6> [132.120811] i915 0000:00:02.0: [drm] GT0: GUC: SLPC enabled
<6> [132.154862] i915: Running intel_workarounds_live_selftests/live_isolated_whitelist
<6> [132.182988] i915: Running intel_workarounds_live_selftests/live_gpu_reset_workarounds
<6> [132.183019] Verifying after GPU reset...
<7> [132.183048] MCR Steering: Default steering: group=0x0, instance=0x0
<7> [132.183080] i915 0000:00:02.0: [drm:wa_init_finish [i915]] GT0: Initialized 5 GT_REF workarounds on global
<7> [132.183585] i915 0000:00:02.0: [drm:wa_init_finish [i915]] GT0: Initialized 10 REF workarounds on rcs0
<7> [132.184101] i915 0000:00:02.0: [drm:wa_init_finish [i915]] GT0: Initialized 5 CTX_REF workarounds on rcs0
<7> [132.184719] i915 0000:00:02.0: [drm:wa_init_finish [i915]] GT0: Initialized 1 REF workarounds on bcs0
<7> [132.185227] i915 0000:00:02.0: [drm:wa_init_finish [i915]] GT0: Initialized 1 CTX_REF workarounds on bcs0
<7> [132.185887] i915 0000:00:02.0: [drm:wa_init_finish [i915]] GT0: Initialized 1 REF workarounds on vcs0
<7> [132.186485] i915 0000:00:02.0: [drm:wa_init_finish [i915]] GT0: Initialized 1 REF workarounds on vcs1
<7> [132.187182] i915 0000:00:02.0: [drm:wa_init_finish [i915]] GT0: Initialized 1 REF workarounds on vecs0
<5> [132.204653] i915 0000:00:02.0: [drm] GT0: Resetting chip for live_workarounds
<6> [132.206056] i915 0000:00:02.0: [drm] GT0: GuC firmware i915/tgl_guc_70.bin version 70.13.0
<6> [132.206062] i915 0000:00:02.0: [drm] GT0: HuC firmware i915/tgl_huc.bin version 7.9.3
<7> [132.212777] i915 0000:00:02.0: [drm:intel_guc_fw_upload [i915]] GT0: GUC: init took 0ms, freq = 1350MHz, before = 1350MHz, status = 0x8002F0EC, count = 0, ret = 0
<7> [132.216290] i915 0000:00:02.0: [drm:guc_enable_communication [i915]] GT0: GUC: communication enabled
<6> [132.218529] i915 0000:00:02.0: [drm] GT0: HuC: authenticated for all workloads
<6> [132.222007] i915 0000:00:02.0: [drm] GT0: GUC: submission enabled
<6> [132.222009] i915 0000:00:02.0: [drm] GT0: GUC: SLPC enabled
<6> [132.257758] i915: Running intel_workarounds_live_selftests/live_engine_reset_workarounds
<7> [132.257790] MCR Steering: Default steering: group=0x0, instance=0x0
<7> [132.257810] i915 0000:00:02.0: [drm:wa_init_finish [i915]] GT0: Initialized 5 GT_REF workarounds on global
<7> [132.258126] i915 0000:00:02.0: [drm:wa_init_finish [i915]] GT0: Initialized 10 REF workarounds on rcs0
<7> [132.258410] i915 0000:00:02.0: [drm:wa_init_finish [i915]] GT0: Initialized 5 CTX_REF workarounds on rcs0
<7> [132.258669] i915 0000:00:02.0: [drm:wa_init_finish [i915]] GT0: Initialized 1 REF workarounds on bcs0
<7> [132.258974] i915 0000:00:02.0: [drm:wa_init_finish [i915]] GT0: Initialized 1 CTX_REF workarounds on bcs0
<7> [132.259227] i915 0000:00:02.0: [drm:wa_init_finish [i915]] GT0: Initialized 1 REF workarounds on vcs0
<7> [132.259484] i915 0000:00:02.0: [drm:wa_init_finish [i915]] GT0: Initialized 1 REF workarounds on vcs1
<7> [132.259752] i915 0000:00:02.0: [drm:wa_init_finish [i915]] GT0: Initialized 1 REF workarounds on vecs0
<6> [132.259970] Verifying after rcs0 reset...
<7> [132.279583] i915 0000:00:02.0: [drm:intel_guc_context_reset_process_msg [i915]] GT0: GUC: Got context reset notification: 0x1004 on rcs0, exiting = no, banned = no
<6> [132.326573] i915 0000:00:02.0: [drm] GPU HANG: ecode 12:0:00000000
<6> [132.345627] Verifying after bcs0 reset...
<7> [132.364779] i915 0000:00:02.0: [drm:intel_guc_context_reset_process_msg [i915]] GT0: GUC: Got context reset notification: 0x1004 on bcs0, exiting = no, banned = no
<6> [132.404999] i915 0000:00:02.0: [drm] GPU HANG: ecode 12:0:00000000
<6> [132.422894] Verifying after vcs0 reset...
<7> [132.440923] i915 0000:00:02.0: [drm:intel_guc_context_reset_process_msg [i915]] GT0: GUC: Got context reset notification: 0x1004 on vcs0, exiting = no, banned = no
<6> [132.482048] i915 0000:00:02.0: [drm] GPU HANG: ecode 12:0:00000000
<6> [132.498798] Verifying after vcs1 reset...
<7> [132.516806] i915 0000:00:02.0: [drm:intel_guc_context_reset_process_msg [i915]] GT0: GUC: Got context reset notification: 0x1007 on vcs1, exiting = no, banned = no
<6> [132.562634] i915 0000:00:02.0: [drm] GPU HANG: ecode 12:0:00000000
<6> [132.579383] Verifying after vecs0 reset...
<7> [132.597474] i915 0000:00:02.0: [drm:intel_guc_context_reset_process_msg [i915]] GT0: GUC: Got context reset notification: 0x1004 on vecs0, exiting = no, banned = no
<6> [132.641944] i915 0000:00:02.0: [drm] GPU HANG: ecode 12:0:00000000
<7> [132.681888] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling DC_off
<7> [132.682549] i915 0000:00:02.0: [drm:gen9_set_dc_state.part.0 [i915]] Setting DC state from 02 to 00
<7> [132.683869] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling PW_2
<7> [132.683979] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling PW_3
<7> [132.684129] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling PW_4
<7> [132.684232] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling PW_5
<7> [132.713304] intel_gt_set_wedged called from intel_gt_set_wedged_on_fini+0xd/0x30 [i915]
<7> [132.760437] i915 0000:00:02.0: [drm:drm_client_release] drm_fb_helper
<4> [132.811486] i915: probe of 0000:00:02.0 failed with error -25
<6> [132.978028] [IGT] i915_selftest: finished subtest workarounds, SUCCESS