<6> [387.750089] [IGT] kms_pipe_crc_basic: starting dynamic subtest pipe-C-DP-2
<7> [387.750437] i915 0000:00:02.0: [drm:drm_mode_addfb2] [FB:126]
<7> [387.751834] [drm:drm_mode_setcrtc] [CRTC:51:pipe A]
<7> [387.753053] [drm:drm_mode_setcrtc] [CRTC:72:pipe B]
<7> [387.754236] [drm:drm_mode_setcrtc] [CRTC:93:pipe C]
<7> [387.754261] [drm:drm_mode_setcrtc] [CONNECTOR:119:DP-2]
<7> [387.754316] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CONNECTOR:119:DP-2] Limiting display bpp to 24 (EDID bpp 0, max requested bpp 36, max platform bpp 36)
<7> [387.754425] i915 0000:00:02.0: [drm:intel_dp_compute_link_config [i915]] DP link computation with max lane count 2 max rate 270000 max bpp 24 pixel clock 25175KHz
<7> [387.754520] i915 0000:00:02.0: [drm:intel_dp_compute_link_config [i915]] DP lane count 1 clock 162000 bpp 24
<7> [387.754612] i915 0000:00:02.0: [drm:intel_dp_compute_link_config [i915]] DP link rate required 75525 available 162000
<7> [387.754706] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CRTC:93:pipe C] hw max bpp: 24, pipe bpp: 24, dithering: 0
<7> [387.754801] i915 0000:00:02.0: [drm:intel_ddi_compute_config_late [i915]] [ENCODER:118:DDI E/PHY E] [CRTC:93:pipe C]
<7> [387.754894] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.enable (expected 0, found 1)
<7> [387.755003] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.active (expected 0, found 1)
<7> [387.755119] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in cpu_transcoder (expected -1, found 2)
<7> [387.755235] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in lane_count (expected 0, found 1)
<7> [387.755331] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in dp_m_n (expected tu 0 data 0/0 link 0/0, or tu 0 data 0/0 link 0/0, found tu 64, data 3910800/8388608 link 81475/524288)
<7> [387.755427] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in output_types (expected 0x00000000, found 0x00000080)
<7> [387.755521] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in framestart_delay (expected 0, found 1)
<7> [387.755615] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.pipe_mode.crtc_hdisplay (expected 0, found 640)
<7> [387.755710] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.pipe_mode.crtc_htotal (expected 0, found 800)
<7> [387.755804] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.pipe_mode.crtc_hblank_start (expected 0, found 640)
<7> [387.755898] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.pipe_mode.crtc_hblank_end (expected 0, found 800)
<7> [387.756002] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.pipe_mode.crtc_hsync_start (expected 0, found 656)
<7> [387.756115] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.pipe_mode.crtc_hsync_end (expected 0, found 752)
<7> [387.756220] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.pipe_mode.crtc_vdisplay (expected 0, found 480)
<7> [387.756314] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.pipe_mode.crtc_vtotal (expected 0, found 525)
<7> [387.756409] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.pipe_mode.crtc_vblank_start (expected 0, found 480)
<7> [387.756504] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.pipe_mode.crtc_vblank_end (expected 0, found 525)
<7> [387.756598] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.pipe_mode.crtc_vsync_start (expected 0, found 490)
<7> [387.756691] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.pipe_mode.crtc_vsync_end (expected 0, found 492)
<7> [387.756785] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.adjusted_mode.crtc_hdisplay (expected 0, found 640)
<7> [387.756879] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.adjusted_mode.crtc_htotal (expected 0, found 800)
<7> [387.756984] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.adjusted_mode.crtc_hblank_start (expected 0, found 640)
<7> [387.757097] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.adjusted_mode.crtc_hblank_end (expected 0, found 800)
<7> [387.757219] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.adjusted_mode.crtc_hsync_start (expected 0, found 656)
<7> [387.757313] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.adjusted_mode.crtc_hsync_end (expected 0, found 752)
<7> [387.757408] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.adjusted_mode.crtc_vdisplay (expected 0, found 480)
<7> [387.757501] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.adjusted_mode.crtc_vtotal (expected 0, found 525)
<7> [387.757595] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.adjusted_mode.crtc_vblank_start (expected 0, found 480)
<7> [387.757688] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.adjusted_mode.crtc_vblank_end (expected 0, found 525)
<7> [387.757782] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.adjusted_mode.crtc_vsync_start (expected 0, found 490)
<7> [387.757875] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.adjusted_mode.crtc_vsync_end (expected 0, found 492)
<7> [387.757984] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in pixel_multiplier (expected 0, found 1)
<7> [387.758099] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.adjusted_mode.flags (2) (expected 0, found 2)
<7> [387.758202] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.adjusted_mode.flags (8) (expected 0, found 8)
<7> [387.758297] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in pipe_bpp (expected 0, found 24)
<7> [387.758392] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.pipe_mode.crtc_clock (expected 0, found 25175)
<7> [387.758486] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.adjusted_mode.crtc_clock (expected 0, found 25175)
<7> [387.758579] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in port_clock (expected 0, found 162000)
<7> [387.758692] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [CRTC:93:pipe C] dbuf slices 0x0 -> 0x1, ddb (0 - 0) -> (0 - 892), active pipes 0x0 -> 0x4
<7> [387.758807] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:73:plane 1C] ddb ( 0 - 0) -> ( 0 - 860), size 0 -> 860
<7> [387.758914] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:89:cursor C] ddb ( 0 - 0) -> ( 860 - 892), size 0 -> 32
<7> [387.759009] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:73:plane 1C] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm, swm, stwm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm, swm, stwm
<7> [387.759103] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:73:plane 1C] lines 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 1, 1, 2, 2, 3, 3, 4, 0, 0, 0
<7> [387.759228] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:73:plane 1C] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 2, 7, 8, 9, 14, 18, 19, 22, 0, 0, 0
<7> [387.759340] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:73:plane 1C] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 3, 8, 9, 10, 15, 19, 20, 23, 0, 0, 0
<7> [387.759449] i915 0000:00:02.0: [drm:intel_plane_calc_min_cdclk [i915]] [PLANE:73:plane 1C] min cdclk (25175 kHz) > [CRTC:93:pipe C] min cdclk (0 kHz)
<7> [387.759545] i915 0000:00:02.0: [drm:intel_bw_calc_min_cdclk [i915]] new bandwidth min cdclk (1574 kHz) > old min cdclk (0 kHz)
<7> [387.759641] i915 0000:00:02.0: [drm:intel_modeset_calc_cdclk [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
<7> [387.759736] i915 0000:00:02.0: [drm:intel_modeset_calc_cdclk [i915]] New voltage level calculated to be logical 0, actual 0
<7> [387.759832] i915 0000:00:02.0: [drm:intel_find_shared_dpll [i915]] [CRTC:93:pipe C] allocated DPLL 1
<7> [387.759937] i915 0000:00:02.0: [drm:skl_get_dpll [i915]] [CRTC:93:pipe C] reserving DPLL 1
<7> [387.760055] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] [CRTC:93:pipe C] enable: yes [modeset]
<7> [387.760155] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] active: yes, output_types: DP (0x80), output format: RGB
<7> [387.760250] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
<7> [387.760344] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] MST master transcoder: <invalid>
<7> [387.760437] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] port sync: master transcoder: <invalid>, slave transcoder bitmask = 0x0
<7> [387.760532] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] bigjoiner: no, pipes: 0x0
<7> [387.760625] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] splitter: disabled, link count 0, overlap 0
<7> [387.760718] i915 0000:00:02.0: [drm:intel_dump_m_n_config.isra.4 [i915]] dp m_n: lanes: 1; data_m: 3910800, data_n: 8388608, link_m: 81475, link_n: 524288, tu: 64
<7> [387.760812] i915 0000:00:02.0: [drm:intel_dump_m_n_config.isra.4 [i915]] dp m2_n2: lanes: 1; data_m: 0, data_n: 0, link_m: 0, link_n: 0, tu: 0
<7> [387.760915] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] framestart delay: 1, MSA timing delay: 0
<7> [387.761027] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] audio: 0, infoframes: 0, infoframes enabled: 0x0
<7> [387.761141] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] vrr: no, vmin: 0, vmax: 0, pipeline full: 0, guardband: 0 flipline: 0, vmin vblank: -1, vmax vblank: -2
<7> [387.761237] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] requested mode: "640x480": 60 25175 640 656 752 800 480 490 492 525 0x48 0xa
<7> [387.761332] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] adjusted mode: "640x480": 60 25175 640 656 752 800 480 490 492 525 0x48 0xa
<7> [387.761427] i915 0000:00:02.0: [drm:intel_dump_crtc_timings [i915]] crtc timings: 25175 640 656 752 800 480 490 492 525, type: 0x48 flags: 0xa
<7> [387.761521] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] pipe mode: "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
<7> [387.761615] i915 0000:00:02.0: [drm:intel_dump_crtc_timings [i915]] crtc timings: 25175 640 656 752 800 480 490 492 525, type: 0x40 flags: 0xa
<7> [387.761710] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] port clock: 162000, pipe src: 640x480+0+0, pixel rate 25175
<7> [387.761804] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] linetime: 255, ips linetime: 0
<7> [387.761897] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1, scaling_filter: 0
<7> [387.762048] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] pch pfit: 0x0+0+0, disabled, force thru: no
<7> [387.762176] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] ips: 0, double wide: 0, drrs: 0
<7> [387.762282] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
<7> [387.762376] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] csc_mode: 0x2 gamma_mode: 0x0 gamma_enable: 0 csc_enable: 0
<7> [387.762470] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] degamma lut: 0 entries, gamma lut: 0 entries
<7> [387.762564] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] [PLANE:73:plane 1C] fb: [FB:126] 640x480 format = XR24 little-endian (0x34325258) modifier = 0x0, visible: yes
<7> [387.762659] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] rotation: 0x1, scaler: -1, scaling_filter: 0
<7> [387.762753] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] src: 640.000000x480.000000+0.000000+0.000000 dst: 640x480+0+0
<7> [387.762848] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] [PLANE:81:plane 2C] fb: [NOFB], visible: no
<7> [387.762949] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] [PLANE:89:cursor C] fb: [NOFB], visible: no
<7> [387.763261] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling always-on
<7> [387.763369] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling DC_off
<7> [387.763731] i915 0000:00:02.0: [drm:gen9_set_dc_state.part.15 [i915]] Setting DC state from 02 to 00
<7> [387.764263] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling PW_2
<7> [387.764427] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:94:DDI B/PHY B]
<7> [387.764524] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:103:DDI C/PHY C]
<7> [387.764618] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:107:DDI D/PHY D]
<7> [387.764711] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:109:DP-MST A]
<7> [387.764804] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:110:DP-MST B]
<7> [387.764897] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:111:DP-MST C]
<7> [387.764997] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:118:DDI E/PHY E]
<7> [387.765108] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.36 [i915]] DPLL 0
<7> [387.765239] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.36 [i915]] DPLL 1
<7> [387.765338] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.36 [i915]] DPLL 2
<7> [387.765437] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.36 [i915]] DPLL 3
<7> [387.765542] i915 0000:00:02.0: [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 0x4, on? 0) for [CRTC:93:pipe C]
<7> [387.765636] i915 0000:00:02.0: [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
<7> [387.765831] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling DDI_IO_A_E
<7> [387.765960] i915 0000:00:02.0: [drm:hsw_set_signal_levels [i915]] Using signal levels 00000000
<7> [387.767259] i915 0000:00:02.0: [drm:drm_dp_read_dpcd_caps [drm_display_helper]] AUX A/DDI E/PHY E: DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00
<7> [387.767915] i915 0000:00:02.0: [drm:intel_dp_start_link_train [i915]] [ENCODER:118:DDI E/PHY E] Using LINK_BW_SET value 06
<7> [387.768427] i915 0000:00:02.0: [drm:intel_dp_set_signal_levels [i915]] [ENCODER:118:DDI E/PHY E][DPRX] 8b/10b, lanes: 1, vswing levels: 0/0/0/0, pre-emphasis levels: 0/0/0/0
<7> [387.768525] i915 0000:00:02.0: [drm:hsw_set_signal_levels [i915]] Using signal levels 00000000
<7> [387.768620] i915 0000:00:02.0: [drm:intel_dp_program_link_training_pattern [i915]] [ENCODER:118:DDI E/PHY E][DPRX] Using DP training pattern TPS1
<7> [387.769536] i915 0000:00:02.0: [drm:intel_dp_link_train_phy [i915]] [ENCODER:118:DDI E/PHY E][DPRX] Clock recovery OK
<7> [387.769631] i915 0000:00:02.0: [drm:intel_dp_program_link_training_pattern [i915]] [ENCODER:118:DDI E/PHY E][DPRX] Using DP training pattern TPS2
<7> [387.771157] i915 0000:00:02.0: [drm:intel_dp_link_train_phy [i915]] [ENCODER:118:DDI E/PHY E][DPRX] Channel EQ done. DP Training successful
<7> [387.771252] i915 0000:00:02.0: [drm:intel_dp_link_train_phy [i915]] [CONNECTOR:119:DP-2][ENCODER:118:DDI E/PHY E][DPRX] Link Training passed at link rate = 162000, lane count = 1
<7> [387.771897] i915 0000:00:02.0: [drm:intel_enable_transcoder [i915]] enabling pipe C
<7> [387.789002] i915 0000:00:02.0: [drm:verify_connector_state [i915]] [CONNECTOR:119:DP-2]
<7> [387.789139] i915 0000:00:02.0: [drm:intel_modeset_verify_crtc [i915]] [CRTC:93:pipe C]
<7> [387.789337] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.36 [i915]] DPLL 1
<7> [387.822409] i915 0000:00:02.0: [drm:i915_fifo_underrun_reset_write [i915]] Re-arming FIFO underruns on pipe C
<7> [387.822619] i915 0000:00:02.0: [drm:i915_fifo_underrun_reset_write [i915]] Re-arming FIFO underruns on pipe C
<7> [387.939154] i915 0000:00:02.0: [drm:drm_mode_rmfb_work_fn] Removing [FB:126] from all active usage due to RMFB ioctl
<7> [387.939189] i915 0000:00:02.0: [drm:atomic_remove_fb] Disabling [PLANE:73:plane 1C] because [FB:126] is removed
<7> [387.939225] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:73:plane 1C] ddb ( 0 - 860) -> ( 0 - 0), size 860 -> 0
<7> [387.939339] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:73:plane 1C] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm, swm, stwm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm, swm, stwm
<7> [387.939443] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:73:plane 1C] lines 0, 1, 1, 2, 2, 3, 3, 4, 0, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
<7> [387.939546] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:73:plane 1C] blocks 2, 7, 8, 9, 14, 18, 19, 22, 0, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
<7> [387.939647] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:73:plane 1C] min_ddb 3, 8, 9, 10, 15, 19, 20, 23, 0, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
<7> [387.956454] i915 0000:00:02.0: [drm:drm_mode_addfb2] [FB:126]
<7> [387.957424] [drm:drm_mode_setcrtc] [CRTC:93:pipe C]
<7> [387.957455] [drm:drm_mode_setcrtc] [CONNECTOR:119:DP-2]
<7> [387.957521] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:73:plane 1C] ddb ( 0 - 0) -> ( 0 - 860), size 0 -> 860
<7> [387.957625] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:73:plane 1C] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm, swm, stwm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm, swm, stwm
<7> [387.957721] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:73:plane 1C] lines 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 1, 1, 2, 2, 3, 3, 4, 0, 0, 0
<7> [387.957816] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:73:plane 1C] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 2, 7, 8, 9, 14, 18, 19, 22, 0, 0, 0
<7> [387.957921] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:73:plane 1C] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 3, 8, 9, 10, 15, 19, 20, 23, 0, 0, 0
<7> [387.972635] i915 0000:00:02.0: [drm:i915_fifo_underrun_reset_write [i915]] Re-arming FIFO underruns on pipe C
<7> [388.089668] i915 0000:00:02.0: [drm:drm_mode_rmfb_work_fn] Removing [FB:126] from all active usage due to RMFB ioctl
<7> [388.089755] i915 0000:00:02.0: [drm:atomic_remove_fb] Disabling [PLANE:73:plane 1C] because [FB:126] is removed
<7> [388.089900] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:73:plane 1C] ddb ( 0 - 860) -> ( 0 - 0), size 860 -> 0
<7> [388.090448] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:73:plane 1C] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm, swm, stwm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm, swm, stwm
<7> [388.091060] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:73:plane 1C] lines 0, 1, 1, 2, 2, 3, 3, 4, 0, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
<7> [388.091612] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:73:plane 1C] blocks 2, 7, 8, 9, 14, 18, 19, 22, 0, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
<7> [388.092108] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:73:plane 1C] min_ddb 3, 8, 9, 10, 15, 19, 20, 23, 0, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
<7> [388.107225] [drm:drm_mode_setcrtc] [CRTC:93:pipe C]
<7> [388.107538] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.enable (expected 1, found 0)
<7> [388.108135] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.active (expected 1, found 0)
<7> [388.108646] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in cpu_transcoder (expected 2, found -1)
<7> [388.109188] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in lane_count (expected 1, found 0)
<7> [388.109691] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in output_types (expected 0x00000080, found 0x00000000)
<7> [388.110220] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in framestart_delay (expected 1, found 0)
<7> [388.110717] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.pipe_mode.crtc_hdisplay (expected 640, found 0)
<7> [388.111276] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.pipe_mode.crtc_htotal (expected 800, found 0)
<7> [388.111841] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.pipe_mode.crtc_hblank_start (expected 640, found 0)
<7> [388.112044] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.pipe_mode.crtc_hblank_end (expected 800, found 0)
<7> [388.112147] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.pipe_mode.crtc_hsync_start (expected 656, found 0)
<7> [388.112249] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.pipe_mode.crtc_hsync_end (expected 752, found 0)
<7> [388.112351] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.pipe_mode.crtc_vdisplay (expected 480, found 0)
<7> [388.112453] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.pipe_mode.crtc_vtotal (expected 525, found 0)
<7> [388.112554] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.pipe_mode.crtc_vblank_start (expected 480, found 0)
<7> [388.112656] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.pipe_mode.crtc_vblank_end (expected 525, found 0)
<7> [388.112757] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.pipe_mode.crtc_vsync_start (expected 490, found 0)
<7> [388.112858] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.pipe_mode.crtc_vsync_end (expected 492, found 0)
<7> [388.112965] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.adjusted_mode.crtc_hdisplay (expected 640, found 0)
<7> [388.113067] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.adjusted_mode.crtc_htotal (expected 800, found 0)
<7> [388.113169] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.adjusted_mode.crtc_hblank_start (expected 640, found 0)
<7> [388.113270] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.adjusted_mode.crtc_hblank_end (expected 800, found 0)
<7> [388.113371] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.adjusted_mode.crtc_hsync_start (expected 656, found 0)
<7> [388.113474] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.adjusted_mode.crtc_hsync_end (expected 752, found 0)
<7> [388.113576] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.adjusted_mode.crtc_vdisplay (expected 480, found 0)
<7> [388.113678] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.adjusted_mode.crtc_vtotal (expected 525, found 0)
<7> [388.113780] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.adjusted_mode.crtc_vblank_start (expected 480, found 0)
<7> [388.113882] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.adjusted_mode.crtc_vblank_end (expected 525, found 0)
<7> [388.113990] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.adjusted_mode.crtc_vsync_start (expected 490, found 0)
<7> [388.114092] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.adjusted_mode.crtc_vsync_end (expected 492, found 0)
<7> [388.114194] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in pixel_multiplier (expected 1, found 0)
<7> [388.114296] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.adjusted_mode.flags (2) (expected 2, found 0)
<7> [388.114398] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.adjusted_mode.flags (8) (expected 8, found 0)
<7> [388.114500] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in pipe_bpp (expected 24, found 0)
<7> [388.114625] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.pipe_mode.crtc_clock (expected 25175, found 0)
<7> [388.114728] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.adjusted_mode.crtc_clock (expected 25175, found 0)
<7> [388.114829] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in port_clock (expected 162000, found 0)
<7> [388.114970] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CRTC:93:pipe C] releasing DPLL 1
<7> [388.115088] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [CRTC:93:pipe C] dbuf slices 0x1 -> 0x0, ddb (0 - 892) -> (0 - 0), active pipes 0x4 -> 0x0
<7> [388.115211] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:89:cursor C] ddb ( 860 - 892) -> ( 0 - 0), size 32 -> 0
<7> [388.115328] i915 0000:00:02.0: [drm:intel_modeset_calc_cdclk [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
<7> [388.115431] i915 0000:00:02.0: [drm:intel_modeset_calc_cdclk [i915]] New voltage level calculated to be logical 0, actual 0
<7> [388.115535] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] [CRTC:93:pipe C] enable: no [modeset]
<7> [388.115638] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] [PLANE:73:plane 1C] fb: [NOFB], visible: no
<7> [388.115739] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] [PLANE:81:plane 2C] fb: [NOFB], visible: no
<7> [388.115841] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] [PLANE:89:cursor C] fb: [NOFB], visible: no
<7> [388.116037] i915 0000:00:02.0: [drm:intel_disable_transcoder [i915]] disabling pipe C
<7> [388.122961] i915 0000:00:02.0: [drm:intel_power_well_disable [i915]] disabling DDI_IO_A_E
<7> [388.123080] i915 0000:00:02.0: [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 0x4, on? 1) for [CRTC:93:pipe C]
<7> [388.123193] i915 0000:00:02.0: [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
<7> [388.123300] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:94:DDI B/PHY B]
<7> [388.123402] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:103:DDI C/PHY C]
<7> [388.123502] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:107:DDI D/PHY D]
<7> [388.123603] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:109:DP-MST A]
<7> [388.123702] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:110:DP-MST B]
<7> [388.123801] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:111:DP-MST C]
<7> [388.123943] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:118:DDI E/PHY E]
<7> [388.124052] i915 0000:00:02.0: [drm:verify_connector_state [i915]] [CONNECTOR:119:DP-2]
<7> [388.124162] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.36 [i915]] DPLL 0
<7> [388.124270] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.36 [i915]] DPLL 1
<7> [388.124376] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.36 [i915]] DPLL 2
<7> [388.124481] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.36 [i915]] DPLL 3
<7> [388.124599] i915 0000:00:02.0: [drm:intel_power_well_disable [i915]] disabling PW_2
<7> [388.124729] i915 0000:00:02.0: [drm:intel_modeset_verify_crtc [i915]] [CRTC:93:pipe C]
<7> [388.124846] i915 0000:00:02.0: [drm:intel_power_well_disable [i915]] disabling DC_off
<7> [388.124965] i915 0000:00:02.0: [drm:skl_enable_dc6 [i915]] Enabling DC6
<7> [388.125070] i915 0000:00:02.0: [drm:gen9_set_dc_state.part.15 [i915]] Setting DC state from 00 to 02
<7> [388.125581] i915 0000:00:02.0: [drm:intel_power_well_disable [i915]] disabling always-on
<7> [388.157176] i915 0000:00:02.0: [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x02000000, dig 0x00000011, pins 0x00000100, long 0x00000000
<7> [388.157326] i915 0000:00:02.0: [drm:intel_hpd_irq_handler [i915]] digital hpd on [ENCODER:118:DDI E/PHY E] - short
<7> [388.157855] i915 0000:00:02.0: [drm:intel_dp_hpd_pulse [i915]] got hpd irq on [ENCODER:118:DDI E/PHY E] - short
<7> [388.158578] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling always-on
<7> [388.158864] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling DC_off
<7> [388.159624] i915 0000:00:02.0: [drm:gen9_set_dc_state.part.15 [i915]] Setting DC state from 02 to 00
<7> [388.161200] i915 0000:00:02.0: [drm:drm_dp_read_dpcd_caps [drm_display_helper]] AUX A/DDI E/PHY E: DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00
<7> [388.161815] i915 0000:00:02.0: [drm:drm_dp_read_desc [drm_display_helper]] AUX A/DDI E/PHY E: DP branch: OUI 00-00-00 dev-ID HW-rev 0.0 SW-rev 0.0 quirks 0x0000
<7> [388.162756] i915 0000:00:02.0: [drm:drm_dp_read_downstream_info [drm_display_helper]] AUX A/DDI E/PHY E: DPCD DFP: 09
<6> [388.257820] PM: suspend entry (deep)
<7> [388.266158] i915 0000:00:02.0: [drm:intel_power_well_disable [i915]] disabling DC_off
<7> [388.266291] i915 0000:00:02.0: [drm:skl_enable_dc6 [i915]] Enabling DC6
<7> [388.266399] i915 0000:00:02.0: [drm:gen9_set_dc_state.part.15 [i915]] Setting DC state from 00 to 02
<7> [388.266926] i915 0000:00:02.0: [drm:intel_power_well_disable [i915]] disabling always-on
<6> [388.294825] Filesystems sync: 0.037 seconds