<6> [132.499744] [IGT] kms_cursor_crc: starting dynamic subtest pipe-C-eDP-1
<7> [132.500941] i915 0000:00:02.0: [drm:drm_mode_addfb2] [FB:365]
<7> [132.501004] i915 0000:00:02.0: [drm:drm_mode_addfb2] [FB:366]
<7> [132.501091] i915 0000:00:02.0: [drm:drm_mode_addfb2] [FB:367]
<7> [132.501663] [drm:drm_mode_setcrtc] [CRTC:98:pipe A]
<7> [132.505475] [drm:drm_mode_setcrtc] [CRTC:167:pipe B]
<7> [132.508949] [drm:drm_mode_setcrtc] [CRTC:236:pipe C]
<7> [132.508988] [drm:drm_mode_setcrtc] [CONNECTOR:308:eDP-1]
<7> [132.509064] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CONNECTOR:308:eDP-1] Limiting display bpp to 18 (EDID bpp 18, max requested bpp 36, max platform bpp 36)
<7> [132.509172] i915 0000:00:02.0: [drm:intel_dp_compute_link_config [i915]] DP link computation with max lane count 2 max rate 270000 max bpp 18 pixel clock 214000KHz
<7> [132.509263] i915 0000:00:02.0: [drm:intel_dp_compute_link_config [i915]] DP lane count 2 clock 270000 bpp 18
<7> [132.509348] i915 0000:00:02.0: [drm:intel_dp_compute_link_config [i915]] DP link rate required 481500 available 540000
<7> [132.509432] i915 0000:00:02.0: [drm:intel_psr_compute_config [i915]] PSR2 not supported in transcoder C
<7> [132.509519] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CRTC:236:pipe C] hw max bpp: 18, pipe bpp: 18, dithering: 1
<7> [132.509604] i915 0000:00:02.0: [drm:intel_ddi_compute_config_late [i915]] [ENCODER:307:DDI A/PHY A] [CRTC:236:pipe C]
<7> [132.509686] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:236:pipe C] fastset mismatch in hw.enable (expected 0, found 1)
<7> [132.509771] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:236:pipe C] fastset mismatch in hw.active (expected 0, found 1)
<7> [132.509853] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:236:pipe C] fastset mismatch in cpu_transcoder (expected -1, found 2)
<7> [132.509935] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:236:pipe C] fastset mismatch in lane_count (expected 0, found 2)
<7> [132.510018] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:236:pipe C] fastset mismatch in dp_m_n (expected tu 0 data 0/0 link 0/0, or tu 0 data 0/0 link 0/0, found tu 64, data 7479842/8388608 link 415546/524288)
<7> [132.510122] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:236:pipe C] fastset mismatch in output_types (expected 0x00000000, found 0x00000100)
<7> [132.510205] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:236:pipe C] fastset mismatch in framestart_delay (expected 0, found 1)
<7> [132.510288] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:236:pipe C] fastset mismatch in hw.pipe_mode.crtc_hdisplay (expected 0, found 1920)
<7> [132.510372] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:236:pipe C] fastset mismatch in hw.pipe_mode.crtc_htotal (expected 0, found 2104)
<7> [132.510457] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:236:pipe C] fastset mismatch in hw.pipe_mode.crtc_hblank_start (expected 0, found 1920)
<7> [132.510543] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:236:pipe C] fastset mismatch in hw.pipe_mode.crtc_hblank_end (expected 0, found 2104)
<7> [132.510630] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:236:pipe C] fastset mismatch in hw.pipe_mode.crtc_hsync_start (expected 0, found 1936)
<7> [132.510713] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:236:pipe C] fastset mismatch in hw.pipe_mode.crtc_hsync_end (expected 0, found 1952)
<7> [132.510797] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:236:pipe C] fastset mismatch in hw.pipe_mode.crtc_vdisplay (expected 0, found 1080)
<7> [132.510879] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:236:pipe C] fastset mismatch in hw.pipe_mode.crtc_vtotal (expected 0, found 1128)
<7> [132.510959] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:236:pipe C] fastset mismatch in hw.pipe_mode.crtc_vblank_start (expected 0, found 1080)
<7> [132.511051] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:236:pipe C] fastset mismatch in hw.pipe_mode.crtc_vblank_end (expected 0, found 1128)
<7> [132.511134] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:236:pipe C] fastset mismatch in hw.pipe_mode.crtc_vsync_start (expected 0, found 1083)
<7> [132.511214] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:236:pipe C] fastset mismatch in hw.pipe_mode.crtc_vsync_end (expected 0, found 1097)
<7> [132.511298] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:236:pipe C] fastset mismatch in hw.adjusted_mode.crtc_hdisplay (expected 0, found 1920)
<7> [132.511383] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:236:pipe C] fastset mismatch in hw.adjusted_mode.crtc_htotal (expected 0, found 2104)
<7> [132.511465] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:236:pipe C] fastset mismatch in hw.adjusted_mode.crtc_hblank_start (expected 0, found 1920)
<7> [132.511547] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:236:pipe C] fastset mismatch in hw.adjusted_mode.crtc_hblank_end (expected 0, found 2104)
<7> [132.511627] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:236:pipe C] fastset mismatch in hw.adjusted_mode.crtc_hsync_start (expected 0, found 1936)
<7> [132.511707] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:236:pipe C] fastset mismatch in hw.adjusted_mode.crtc_hsync_end (expected 0, found 1952)
<7> [132.511787] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:236:pipe C] fastset mismatch in hw.adjusted_mode.crtc_vdisplay (expected 0, found 1080)
<7> [132.511874] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:236:pipe C] fastset mismatch in hw.adjusted_mode.crtc_vtotal (expected 0, found 1128)
<7> [132.511959] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:236:pipe C] fastset mismatch in hw.adjusted_mode.crtc_vblank_start (expected 0, found 1080)
<7> [132.512057] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:236:pipe C] fastset mismatch in hw.adjusted_mode.crtc_vblank_end (expected 0, found 1128)
<7> [132.512141] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:236:pipe C] fastset mismatch in hw.adjusted_mode.crtc_vsync_start (expected 0, found 1083)
<7> [132.512222] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:236:pipe C] fastset mismatch in hw.adjusted_mode.crtc_vsync_end (expected 0, found 1097)
<7> [132.512302] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:236:pipe C] fastset mismatch in pixel_multiplier (expected 0, found 1)
<7> [132.512387] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:236:pipe C] fastset mismatch in hw.adjusted_mode.flags (2) (expected 0, found 2)
<7> [132.512472] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:236:pipe C] fastset mismatch in hw.adjusted_mode.flags (8) (expected 0, found 8)
<7> [132.512558] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:236:pipe C] fastset mismatch in pipe_bpp (expected 0, found 18)
<7> [132.512641] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:236:pipe C] fastset mismatch in hw.pipe_mode.crtc_clock (expected 0, found 214000)
<7> [132.512723] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:236:pipe C] fastset mismatch in hw.adjusted_mode.crtc_clock (expected 0, found 214000)
<7> [132.512808] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:236:pipe C] fastset mismatch in port_clock (expected 0, found 270000)
<7> [132.512925] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] Enabled dbuf slices 0x1 -> 0x3 (total dbuf slices 0x3), mbus joined? no->no
<7> [132.513010] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [CRTC:236:pipe C] dbuf slices 0x0 -> 0x3, ddb (0 - 0) -> (0 - 2048), active pipes 0x0 -> 0x4
<7> [132.513153] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:169:plane 1C] ddb ( 0 - 0) -> ( 0 - 1996), size 0 -> 1996
<7> [132.513239] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:232:cursor C] ddb ( 0 - 0) -> (1996 - 2048), size 0 -> 52
<7> [132.513322] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:169:plane 1C] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm, swm, stwm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7,*twm,*swm,*stwm
<7> [132.513405] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:169:plane 1C] lines 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 1, 7, 8, 8, 11, 13, 13, 15, 0, 5, 0
<7> [132.513487] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:169:plane 1C] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 16, 113, 129, 129, 177, 209, 209, 241, 30, 81, 95
<7> [132.513568] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:169:plane 1C] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 19, 126, 143, 143, 196, 231, 231, 267, 31, 91, 96
<7> [132.513651] i915 0000:00:02.0: [drm:intel_bw_atomic_check [i915]] [CRTC:236:pipe C] data rate 856000 num active planes 1
<7> [132.513739] i915 0000:00:02.0: [drm:intel_bw_atomic_check [i915]] QGV point 0: max bw 12447 required 856
<7> [132.513826] i915 0000:00:02.0: [drm:intel_bw_atomic_check [i915]] QGV point 1: max bw 12447 required 856
<7> [132.513910] i915 0000:00:02.0: [drm:intel_bw_atomic_check [i915]] QGV point 2: max bw 16761 required 856
<7> [132.513993] i915 0000:00:02.0: [drm:intel_bw_atomic_check [i915]] QGV point 3: max bw 14636 required 856
<7> [132.514104] i915 0000:00:02.0: [drm:intel_plane_calc_min_cdclk [i915]] [PLANE:169:plane 1C] min cdclk (107000 kHz) > [CRTC:236:pipe C] min cdclk (0 kHz)
<7> [132.514189] i915 0000:00:02.0: [drm:intel_bw_calc_min_cdclk [i915]] new bandwidth min cdclk (16719 kHz) > old min cdclk (0 kHz)
<7> [132.514273] i915 0000:00:02.0: [drm:intel_modeset_calc_cdclk [i915]] Modeset required for cdclk change
<7> [132.514358] i915 0000:00:02.0: [drm:intel_modeset_calc_cdclk [i915]] New cdclk calculated to be logical 307200 kHz, actual 307200 kHz
<7> [132.514444] i915 0000:00:02.0: [drm:intel_modeset_calc_cdclk [i915]] New voltage level calculated to be logical 0, actual 0
<7> [132.514530] i915 0000:00:02.0: [drm:intel_find_shared_dpll [i915]] [CRTC:236:pipe C] allocated DPLL 0
<7> [132.514614] i915 0000:00:02.0: [drm:icl_get_dplls [i915]] [CRTC:236:pipe C] reserving DPLL 0
<7> [132.514699] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] [CRTC:236:pipe C] enable: yes [modeset]
<7> [132.514785] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] active: yes, output_types: EDP (0x100), output format: RGB
<7> [132.514869] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] cpu_transcoder: C, pipe bpp: 18, dithering: 1
<7> [132.514951] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] MST master transcoder: <invalid>
<7> [132.515048] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] port sync: master transcoder: <invalid>, slave transcoder bitmask = 0x0
<7> [132.515134] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] bigjoiner: no, pipes: 0x0
<7> [132.515219] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] splitter: disabled, link count 0, overlap 0
<7> [132.515302] i915 0000:00:02.0: [drm:intel_dump_m_n_config.isra.4 [i915]] dp m_n: lanes: 2; data_m: 7479842, data_n: 8388608, link_m: 415546, link_n: 524288, tu: 64
<7> [132.515386] i915 0000:00:02.0: [drm:intel_dump_m_n_config.isra.4 [i915]] dp m2_n2: lanes: 2; data_m: 0, data_n: 0, link_m: 0, link_n: 0, tu: 0
<7> [132.515473] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] framestart delay: 1, MSA timing delay: 0
<7> [132.515558] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] audio: 0, infoframes: 0, infoframes enabled: 0x4
<7> [132.515642] i915 0000:00:02.0: DP SDP: VSC, revision 0, length 0
<7> [132.515644] i915 0000:00:02.0: pixelformat: RGB
<7> [132.515646] i915 0000:00:02.0: colorimetry: sRGB
<7> [132.515647] i915 0000:00:02.0: bpc: 0
<7> [132.515648] i915 0000:00:02.0: dynamic range: VESA range
<7> [132.515650] i915 0000:00:02.0: content type: Not defined
<7> [132.515651] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] vrr: no, vmin: 0, vmax: 0, pipeline full: 0, guardband: 0 flipline: 0, vmin vblank: -1, vmax vblank: -2
<7> [132.515734] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] requested mode: "1920x1080": 90 214000 1920 1936 1952 2104 1080 1083 1097 1128 0x48 0xa
<7> [132.515816] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] adjusted mode: "1920x1080": 90 214000 1920 1936 1952 2104 1080 1083 1097 1128 0x48 0xa
<7> [132.515900] i915 0000:00:02.0: [drm:intel_dump_crtc_timings [i915]] crtc timings: 214000 1920 1936 1952 2104 1080 1083 1097 1128, type: 0x48 flags: 0xa
<7> [132.515987] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] pipe mode: "1920x1080": 90 214000 1920 1936 1952 2104 1080 1083 1097 1128 0x40 0xa
<7> [132.516096] i915 0000:00:02.0: [drm:intel_dump_crtc_timings [i915]] crtc timings: 214000 1920 1936 1952 2104 1080 1083 1097 1128, type: 0x40 flags: 0xa
<7> [132.516181] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] port clock: 270000, pipe src: 1920x1080+0+0, pixel rate 214000
<7> [132.516264] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] linetime: 79, ips linetime: 0
<7> [132.516345] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1, scaling_filter: 0
<7> [132.516426] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] pch pfit: 0x0+0+0, disabled, force thru: no
<7> [132.516514] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] ips: 0, double wide: 0, drrs: 0
<7> [132.516599] i915 0000:00:02.0: [drm:icl_dump_hw_state [i915]] dpll_hw_state: cfgcr0: 0xe001a5, cfgcr1: 0x88, div0: 0x0, mg_refclkin_ctl: 0x0, hg_clktop2_coreclkctl1: 0x0, mg_clktop2_hsclkctl: 0x0, mg_pll_div0: 0x0, mg_pll_div2: 0x0, mg_pll_lf: 0x0, mg_pll_frac_lock: 0x0, mg_pll_ssc: 0x0, mg_pll_bias: 0x0, mg_pll_tdc_coldst_bias: 0x0
<7> [132.516688] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] csc_mode: 0x0 gamma_mode: 0x0 gamma_enable: 0 csc_enable: 0
<7> [132.516770] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] degamma lut: 0 entries, gamma lut: 0 entries
<7> [132.516853] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] [PLANE:169:plane 1C] fb: [FB:366] 1920x1080 format = XR24 little-endian (0x34325258) modifier = 0x0, visible: yes
<7> [132.516935] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] rotation: 0x1, scaler: -1, scaling_filter: 0
<7> [132.517015] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] src: 1920.000000x1080.000000+0.000000+0.000000 dst: 1920x1080+0+0
<7> [132.517119] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] [PLANE:178:plane 2C] fb: [NOFB], visible: no
<7> [132.517200] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] [PLANE:187:plane 3C] fb: [NOFB], visible: no
<7> [132.517281] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] [PLANE:196:plane 4C] fb: [NOFB], visible: no
<7> [132.517362] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] [PLANE:205:plane 5C] fb: [NOFB], visible: no
<7> [132.517442] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] [PLANE:214:plane 6C] fb: [NOFB], visible: no
<7> [132.517524] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] [PLANE:223:plane 7C] fb: [NOFB], visible: no
<7> [132.517603] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] [PLANE:232:cursor C] fb: [NOFB], visible: no
<7> [132.520809] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling always-on
<7> [132.520927] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling DC_off
<7> [132.521574] i915 0000:00:02.0: [drm:gen9_set_dc_state.part.15 [i915]] Setting DC state from 02 to 00
<7> [132.522674] i915 0000:00:02.0: [drm:check_phy_reg [i915]] Combo PHY A reg 001628a0 state mismatch: current 900337bc mask e0000000 expected a0000000
<7> [132.522768] i915 0000:00:02.0: [drm:icl_verify_procmon_ref_values [i915]] Combo PHY A Voltage/Process Info : 0.85V dot0 (low-voltage)
<7> [132.522911] i915 0000:00:02.0: [drm:check_phy_reg [i915]] Combo PHY B reg 0006c8a0 state mismatch: current 9003501c mask e0000000 expected a0000000
<7> [132.523001] i915 0000:00:02.0: [drm:icl_verify_procmon_ref_values [i915]] Combo PHY B Voltage/Process Info : 0.85V dot0 (low-voltage)
<7> [132.523158] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling PW_2
<7> [132.523250] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling PW_3
<7> [132.523351] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling PW_4
<7> [132.523463] i915 0000:00:02.0: [drm:intel_cdclk_dump_config [i915]] Changing CDCLK to 307200 kHz, VCO 614400 kHz, ref 38400 kHz, bypass 19200 kHz, voltage level 0
<7> [132.523627] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:307:DDI A/PHY A]
<7> [132.523714] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:316:DDI B/PHY B]
<7> [132.523800] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:325:DDI TC1/PHY TC1]
<7> [132.523885] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:327:DP-MST A]
<7> [132.523967] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:328:DP-MST B]
<7> [132.524066] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:329:DP-MST C]
<7> [132.524146] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:330:DP-MST D]
<7> [132.524227] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:335:DDI TC2/PHY TC2]
<7> [132.524307] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:337:DP-MST A]
<7> [132.524388] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:338:DP-MST B]
<7> [132.524473] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:339:DP-MST C]
<7> [132.524556] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:340:DP-MST D]
<7> [132.524636] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:344:DDI TC3/PHY TC3]
<7> [132.524717] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:346:DP-MST A]
<7> [132.524796] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:347:DP-MST B]
<7> [132.524875] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:348:DP-MST C]
<7> [132.524952] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:349:DP-MST D]
<7> [132.525041] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:353:DDI TC4/PHY TC4]
<7> [132.525119] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:355:DP-MST A]
<7> [132.525197] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:356:DP-MST B]
<7> [132.525276] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:357:DP-MST C]
<7> [132.525359] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:358:DP-MST D]
<7> [132.525442] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.36 [i915]] DPLL 0
<7> [132.525533] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.36 [i915]] DPLL 1
<7> [132.525622] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.36 [i915]] TBT PLL
<7> [132.525713] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.36 [i915]] TC PLL 1
<7> [132.525802] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.36 [i915]] TC PLL 2
<7> [132.525891] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.36 [i915]] TC PLL 3
<7> [132.525978] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.36 [i915]] TC PLL 4
<7> [132.526094] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.36 [i915]] TC PLL 5
<7> [132.526180] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.36 [i915]] TC PLL 6
<7> [132.526266] i915 0000:00:02.0: [drm:gen9_dbuf_slices_update [i915]] Updating dbuf slices to 0x3
<7> [132.526384] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling AUX_A
<7> [132.526470] i915 0000:00:02.0: [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 0x4, on? 0) for [CRTC:236:pipe C]
<7> [132.526553] i915 0000:00:02.0: [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
<7> [132.526692] i915 0000:00:02.0: [drm:intel_pps_on_unlocked [i915]] Turn [ENCODER:307:DDI A/PHY A] panel power on
<7> [132.526801] i915 0000:00:02.0: [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle