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igt@sw_sync@sync_multi_timeline_wait - fail - Failed assertion: active == 2 && signaled == 1, Fence did not signal properly|Failed assertion: signaled == 1, Fence did not signal|Failed assertion: signaled == 1, in_fence[0] did not signal

https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11709/shard-apl6/igt@sw_sync@sync_multi_timeline_wait.html

Starting subtest: sync_multi_timeline_wait
(sw_sync:1174) CRITICAL: Test assertion failure function test_sync_multi_timeline_wait, file ../tests/sw_sync.c:430:
(sw_sync:1174) CRITICAL: Failed assertion: active == 2 && signaled == 1
(sw_sync:1174) CRITICAL: Fence did not signal properly
Subtest sync_multi_timeline_wait failed.
Edited by SAI NANDAN
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