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igt@i915_pm_sseu@full-enable - fail - Failed assertion: stat->hw.slice_total == stat->info.slice_total

https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20215/shard-skl2/igt@i915_pm_sseu@full-enable.html

Starting subtest: full-enable
(i915_pm_sseu:917) CRITICAL: Test assertion failure function check_full_enable, file ../tests/i915/i915_pm_sseu.c:325:
(i915_pm_sseu:917) CRITICAL: Failed assertion: stat->hw.slice_total == stat->info.slice_total
(i915_pm_sseu:917) CRITICAL: error: 0 != 1
Subtest full-enable failed.
**** DEBUG ****
ed EU: no
(i915_pm_sseu:917) DEBUG:   Has Slice Power Gating: no
(i915_pm_sseu:917) DEBUG:   Has Subslice Power Gating: no
(i915_pm_sseu:917) DEBUG:   Has EU Power Gating: yes
(i915_pm_sseu:917) DEBUG: SSEU Device Status
(i915_pm_sseu:917) DEBUG:   Enabled Slice Mask: 0000
(i915_pm_sseu:917) DEBUG:   Enabled Slice Total: 0
(i915_pm_sseu:917) DEBUG:   Enabled Subslice Total: 0
(i915_pm_sseu:917) DEBUG:   Enabled EU Total: 0
(i915_pm_sseu:917) DEBUG:   Enabled EU Per Subslice: 0
(i915_pm_sseu:917) CRITICAL: Test assertion failure function check_full_enable, file ../tests/i915/i915_pm_sseu.c:325:
(i915_pm_sseu:917) CRITICAL: Failed assertion: stat->hw.slice_total == stat->info.slice_total
(i915_pm_sseu:917) CRITICAL: error: 0 != 1
(i915_pm_sseu:917) igt_core-INFO: Stack trace:
(i915_pm_sseu:917) igt_core-INFO:   #0 ../lib/igt_core.c:1745 __igt_fail_assert()
(i915_pm_sseu:917) igt_core-INFO:   #1 ../tests/i915/i915_pm_sseu.c:337 __real_main379()
(i915_pm_sseu:917) igt_core-INFO:   #2 [<unknown>+0x0]
****  END  ****
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