Skip to content

CML : igt@kms_plane_scaling@scaler-with-clipping-clamping@ - skip - Test requirement: get_num_scalers(d, pipe) >= 2

https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_713/fi-cml-u2/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-rotation.html

  • Out
  • Starting dynamic subtest: pipe-C-scaler-with-rotation
  • Test requirement not met in function test_scaler_with_clipping_clamping_scenario, file ../tests/kms_plane_scaling.c:533:
  • Test requirement: get_num_scalers(d, pipe) >= 2
  • Dynamic subtest pipe-C-scaler-with-rotation: SKIP (0.000s)
  • Subtest scaler-with-clipping-clamping: SUCCESS (10.044s)
  • Err
  • Starting dynamic subtest: pipe-C-scaler-with-rotation
  • Dynamic subtest pipe-C-scaler-with-rotation: SKIP (0.000s)
  • Subtest scaler-with-clipping-clamping: SUCCESS (10.044s)
  • Dmesg
  • <6> [377.623128] [IGT] kms_plane_scaling: starting dynamic subtest pipe-C-scaler-with-rotation
  • <6> [377.623284] [IGT] kms_plane_scaling: exiting, ret=0
  • <6> [377.638259] Console: switching to colour frame buffer device 240x67
  • <7> [377.648007] i915 0000:00:02.0: [drm:skl_update_scaler [i915]] scaler_user index 1.4: Staged freeing scaler id 1 scaler_users = 0x8
  • <7> [377.648076] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] ddb ( 0 - 228) -> ( 0 - 860), size 228 -> 860
  • <7> [377.648108] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:60:plane 2B] ddb ( 228 - 860) -> ( 0 - 0), size 632 -> 0
  • <7> [377.648141] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:60:plane 2B] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm, swm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm, swm
  • <7> [377.648173] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:60:plane 2B] lines 0, 16, 16, 16, 16, 16, 16, 16, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
  • <7> [377.648204] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:60:plane 2B] blocks 24, 47, 47, 47, 47, 47, 47, 47, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
  • <7> [377.648236] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:60:plane 2B] min_ddb 25, 48, 48, 48, 48, 48, 48, 48, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
  • <7> [377.648287] i915 0000:00:02.0: [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 1.0 to PLANE:52
  • <7> [377.656234] i915 0000:00:02.0: [drm:skl_update_scaler [i915]] scaler_user index 1.3: Staged freeing scaler id 0 scaler_users = 0x0
  • <7> [377.656295] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] ddb ( 0 - 860) -> ( 0 - 0), size 860 -> 0
  • <7> [377.656332] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm, swm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm, swm
  • <7> [377.656369] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] lines 0, 3, 4, 4, 6, 7, 7, 8, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
  • <7> [377.656405] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] blocks 7, 11, 14, 14, 20, 23, 23, 26, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
  • <7> [377.656441] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] min_ddb 8, 12, 15, 15, 21, 24, 24, 27, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
  • <7> [377.673485] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CONNECTOR:95:eDP-1] Limiting display bpp to 24 instead of EDID bpp 24, requested bpp 36, max platform bpp 36
  • <7> [377.673546] i915 0000:00:02.0: [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max rate 540000 max bpp 24 pixel clock 138500KHz
  • <7> [377.673604] i915 0000:00:02.0: [drm:intel_dp_compute_config [i915]] Force DSC en = 0
  • <7> [377.673686] i915 0000:00:02.0: [drm:intel_dp_compute_config [i915]] DP lane count 2 clock 540000 bpp 24
  • <7> [377.673739] i915 0000:00:02.0: [drm:intel_dp_compute_config [i915]] DP link rate required 415500 available 1080000
  • <7> [377.673792] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] hw max bpp: 24, pipe bpp: 24, dithering: 0
  • <7> [377.673856] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CONNECTOR:114:DP-2] Limiting display bpp to 24 instead of EDID bpp 24, requested bpp 36, max platform bpp 36
  • <7> [377.673907] i915 0000:00:02.0: [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max rate 270000 max bpp 24 pixel clock 148500KHz
  • <7> [377.673957] i915 0000:00:02.0: [drm:intel_dp_compute_config [i915]] Force DSC en = 0
  • <7> [377.674007] i915 0000:00:02.0: [drm:intel_dp_compute_config [i915]] DP lane count 4 clock 162000 bpp 24
  • <7> [377.674056] i915 0000:00:02.0: [drm:intel_dp_compute_config [i915]] DP link rate required 445500 available 648000
  • <7> [377.674107] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] hw max bpp: 24, pipe bpp: 24, dithering: 0
  • <7> [377.674156] i915 0000:00:02.0: [drm:intel_ddi_compute_config_late [i915]] [ENCODER:94:DDI A/PHY A] [CRTC:51:pipe A]
  • <7> [377.674219] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:51:pipe A] fastset mismatch in hw.adjusted_mode.crtc_hdisplay (expected 0, found 1920)
  • <7> [377.674269] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:51:pipe A] fastset mismatch in hw.adjusted_mode.crtc_htotal (expected 0, found 2080)
  • <7> [377.674318] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:51:pipe A] fastset mismatch in hw.adjusted_mode.crtc_hblank_start (expected 0, found 1920)
  • <7> [377.674367] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:51:pipe A] fastset mismatch in hw.adjusted_mode.crtc_hblank_end (expected 0, found 2080)
  • <7> [377.674416] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:51:pipe A] fastset mismatch in hw.adjusted_mode.crtc_hsync_start (expected 0, found 1968)
  • <7> [377.674464] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:51:pipe A] fastset mismatch in hw.adjusted_mode.crtc_hsync_end (expected 0, found 2000)
  • <7> [377.674513] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:51:pipe A] fastset mismatch in hw.adjusted_mode.crtc_vdisplay (expected 0, found 1080)
  • <7> [377.674563] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:51:pipe A] fastset mismatch in hw.adjusted_mode.crtc_vtotal (expected 0, found 1111)
  • <7> [377.674632] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:51:pipe A] fastset mismatch in hw.adjusted_mode.crtc_vblank_start (expected 0, found 1080)
  • <7> [377.674682] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:51:pipe A] fastset mismatch in hw.adjusted_mode.crtc_vblank_end (expected 0, found 1111)
  • <7> [377.674732] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:51:pipe A] fastset mismatch in hw.adjusted_mode.crtc_vsync_start (expected 0, found 1083)
  • <7> [377.674782] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:51:pipe A] fastset mismatch in hw.adjusted_mode.crtc_vsync_end (expected 0, found 1088)
  • <7> [377.674833] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:51:pipe A] fastset mismatch in hw.adjusted_mode.flags (2) (expected 0, found 2)
  • <7> [377.674883] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:51:pipe A] fastset mismatch in hw.adjusted_mode.flags (8) (expected 0, found 8)
  • <7> [377.674934] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:51:pipe A] fastset mismatch in hw.adjusted_mode.crtc_clock (expected 0, found 138500)
  • <7> [377.674985] i915 0000:00:02.0: [drm:intel_ddi_compute_config_late [i915]] [ENCODER:113:DDI C/PHY C] [CRTC:93:pipe C]
  • <7> [377.675036] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.adjusted_mode.crtc_hdisplay (expected 0, found 1920)
  • <7> [377.675086] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.adjusted_mode.crtc_htotal (expected 0, found 2200)
  • <7> [377.675135] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.adjusted_mode.crtc_hblank_start (expected 0, found 1920)
  • <7> [377.675196] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.adjusted_mode.crtc_hblank_end (expected 0, found 2200)
  • <7> [377.675245] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.adjusted_mode.crtc_hsync_start (expected 0, found 2008)
  • <7> [377.675314] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.adjusted_mode.crtc_hsync_end (expected 0, found 2052)
  • <7> [377.675907] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.adjusted_mode.crtc_vdisplay (expected 0, found 1080)
  • <7> [377.675971] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.adjusted_mode.crtc_vtotal (expected 0, found 1125)
  • <7> [377.676032] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.adjusted_mode.crtc_vblank_start (expected 0, found 1080)
  • <7> [377.676093] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.adjusted_mode.crtc_vblank_end (expected 0, found 1125)
  • <7> [377.676162] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.adjusted_mode.crtc_vsync_start (expected 0, found 1084)
  • <7> [377.676224] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.adjusted_mode.crtc_vsync_end (expected 0, found 1089)
  • <7> [377.676284] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.adjusted_mode.flags (1) (expected 0, found 1)
  • <7> [377.676343] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.adjusted_mode.flags (4) (expected 0, found 4)
  • <7> [377.676404] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:93:pipe C] fastset mismatch in hw.adjusted_mode.crtc_clock (expected 0, found 148500)
  • <7> [377.676473] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [CRTC:51:pipe A] dbuf slices 0x1, ddb (0 - 297), active pipes 0x7
  • <7> [377.676517] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [CRTC:72:pipe B] dbuf slices 0x1, ddb (297 - 594), active pipes 0x7
  • <7> [377.676563] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [CRTC:93:pipe C] dbuf slices 0x1, ddb (594 - 892), active pipes 0x7
  • <7> [377.676630] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] ddb ( 0 - 0) -> ( 0 - 273), size 0 -> 273
  • <7> [377.676675] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] ddb ( 0 - 0) -> ( 273 - 297), size 0 -> 24
  • <7> [377.676728] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm, swm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm, swm
  • <7> [377.676781] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] lines 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 2, 3, 3, 5, 6, 6, 7, 0, 0
  • <7> [377.676833] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 8, 27, 37, 41, 75, 90, 97, 114, 0, 0
  • <7> [377.676882] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 9, 28, 38, 42, 76, 91, 98, 115, 0, 0
  • <7> [377.676925] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] ddb ( 0 - 0) -> ( 297 - 570), size 0 -> 273
  • <7> [377.676967] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] ddb ( 860 - 892) -> ( 570 - 594), size 32 -> 24
  • <7> [377.677026] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm, swm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm, swm
  • <7> [377.677070] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] lines 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 2, 3, 3, 5, 6, 6, 7, 0, 0
  • <7> [377.677114] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 8, 29, 40, 44, 80, 96, 98, 114, 0, 0
  • <7> [377.677158] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 9, 30, 41, 45, 81, 97, 99, 115, 0, 0
  • <7> [377.677191] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:73:plane 1C] ddb ( 0 - 0) -> ( 594 - 868), size 0 -> 274
  • <7> [377.677234] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:89:cursor C] ddb ( 0 - 0) -> ( 868 - 892), size 0 -> 24
  • <7> [377.677278] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:73:plane 1C] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm, swm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm, swm
  • <7> [377.677322] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:73:plane 1C] lines 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 2, 3, 3, 5, 6, 6, 7, 0, 0
  • <7> [377.677366] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:73:plane 1C] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 8, 29, 40, 44, 80, 96, 98, 114, 0, 0
  • <7> [377.677410] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:73:plane 1C] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 9, 30, 41, 45, 81, 97, 99, 115, 0, 0
  • <7> [377.677498] i915 0000:00:02.0: [drm:intel_plane_calc_min_cdclk [i915]] [PLANE:31:plane 1A] min cdclk (138500 kHz) > [CRTC:51:pipe A] min cdclk (0 kHz)
  • <7> [377.677563] i915 0000:00:02.0: [drm:intel_plane_calc_min_cdclk [i915]] [PLANE:73:plane 1C] min cdclk (148500 kHz) > [CRTC:93:pipe C] min cdclk (0 kHz)
  • <7> [377.677646] i915 0000:00:02.0: [drm:intel_modeset_calc_cdclk [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
  • <7> [377.677710] i915 0000:00:02.0: [drm:intel_modeset_calc_cdclk [i915]] New voltage level calculated to be logical 0, actual 0
  • <7> [377.677800] i915 0000:00:02.0: [drm:intel_find_shared_dpll [i915]] [CRTC:51:pipe A] allocated DPLL 0
  • <7> [377.677865] i915 0000:00:02.0: [drm:intel_reference_shared_dpll.isra.24 [i915]] using DPLL 0 for pipe A
  • <7> [377.677918] i915 0000:00:02.0: [drm:intel_find_shared_dpll [i915]] [CRTC:93:pipe C] sharing existing DPLL 1 (crtc mask 0x00000002, active 2)
  • <7> [377.677969] i915 0000:00:02.0: [drm:intel_reference_shared_dpll.isra.24 [i915]] using DPLL 1 for pipe C
  • <7> [377.678022] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [CRTC:51:pipe A] enable: yes [modeset]
  • <7> [377.678074] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] active: yes, output_types: EDP (0x100), output format: RGB
  • <7> [377.678126] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
  • <7> [377.678176] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] MST master transcoder:
  • <7> [377.678227] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] port sync: master transcoder: , slave transcoder bitmask = 0x0
  • <7> [377.678277] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] bigjoiner: no
  • <7> [377.678328] i915 0000:00:02.0: [drm:intel_dump_m_n_config.isra.102 [i915]] dp m_n: lanes: 2; gmch_m: 3227283, gmch_n: 8388608, link_m: 268940, link_n: 1048576, tu: 64
  • <7> [377.678378] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0, infoframes enabled: 0x4
  • <7> [377.678383] i915 0000:00:02.0: DP SDP: VSC, revision 0, length 0
  • <7> [377.678386] i915 0000:00:02.0: pixelformat: RGB
  • <7> [377.678389] i915 0000:00:02.0: colorimetry: sRGB
  • <7> [377.678392] i915 0000:00:02.0: bpc: 0
  • <7> [377.678395] i915 0000:00:02.0: dynamic range: VESA range
  • <7> [377.678398] i915 0000:00:02.0: content type: Not defined
  • <7> [377.678448] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] requested mode:
  • <7> [377.678455] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 60 138500 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
  • <7> [377.678504] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] adjusted mode:
  • <7> [377.678509] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 60 138500 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
  • <7> [377.678561] i915 0000:00:02.0: [drm:intel_dump_crtc_timings.isra.103 [i915]] crtc timings: 138500 1920 1968 2000 2080 1080 1083 1088 1111, type: 0x48 flags: 0xa
  • <7> [377.678628] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] pipe mode:
  • <7> [377.678634] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 60 138500 1920 1968 2000 2080 1080 1083 1088 1111 0x40 0xa
  • <7> [377.678685] i915 0000:00:02.0: [drm:intel_dump_crtc_timings.isra.103 [i915]] crtc timings: 138500 1920 1968 2000 2080 1080 1083 1088 1111, type: 0x40 flags: 0xa
  • <7> [377.678737] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 1920x1080, pixel rate 138500
  • <7> [377.678788] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] linetime: 121, ips linetime: 0
  • <7> [377.678839] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
  • <7> [377.678890] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] pch pfit: 0x0+0+0, disabled, force thru: no
  • <7> [377.678941] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
  • <7> [377.678993] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
  • <7> [377.679044] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] csc_mode: 0x2 gamma_mode: 0x0 gamma_enable: 0 csc_enable: 0
  • <7> [377.679110] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] degamma lut: 0 entries, gamma lut: 0 entries
  • <7> [377.679164] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 1A] fb: [FB:127] 1920x1080 format = XR24 little-endian (0x34325258) modifier = 0x0, visible: yes
  • <7> [377.679217] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] rotation: 0x1, scaler: -1
  • <7> [377.679269] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] src: 1920.000000x1080.000000+0.000000+0.000000 dst: 1920x1080+0+0
  • <7> [377.679321] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 2A] fb: [NOFB], visible: no
  • <7> [377.679373] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor A] fb: [NOFB], visible: no
  • <7> [377.679426] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [CRTC:93:pipe C] enable: yes [modeset]
  • <7> [377.679478] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] active: yes, output_types: DP (0x80), output format: RGB
  • <7> [377.679530] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
  • <7> [377.679589] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] MST master transcoder:
  • <7> [377.679657] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] port sync: master transcoder: , slave transcoder bitmask = 0x0
  • <7> [377.679710] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] bigjoiner: no
  • <7> [377.679762] i915 0000:00:02.0: [drm:intel_dump_m_n_config.isra.102 [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
  • <7> [377.679815] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0, infoframes enabled: 0x0
  • <7> [377.679867] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] requested mode:
  • <7> [377.679872] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
  • <7> [377.679924] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] adjusted mode:
  • <7> [377.679929] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
  • <7> [377.679981] i915 0000:00:02.0: [drm:intel_dump_crtc_timings.isra.103 [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
  • <7> [377.680032] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] pipe mode:
  • <7> [377.680037] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
  • <7> [377.680088] i915 0000:00:02.0: [drm:intel_dump_crtc_timings.isra.103 [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x40 flags: 0x5
  • <7> [377.680140] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
  • <7> [377.680192] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] linetime: 119, ips linetime: 0
  • <7> [377.680243] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
  • <7> [377.680296] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] pch pfit: 0x0+0+0, disabled, force thru: no
  • <7> [377.680360] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
  • <7> [377.680412] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
  • <7> [377.680464] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] csc_mode: 0x2 gamma_mode: 0x0 gamma_enable: 0 csc_enable: 0
  • <7> [377.680515] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] degamma lut: 0 entries, gamma lut: 0 entries
  • <7> [377.680572] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [PLANE:73:plane 1C] fb: [FB:127] 1920x1080 format = XR24 little-endian (0x34325258) modifier = 0x0, visible: yes
  • <7> [377.680637] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] rotation: 0x1, scaler: -1
  • <7> [377.680691] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] src: 1920.000000x1080.000000+0.000000+0.000000 dst: 1920x1080+0+0
  • <7> [377.680744] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [PLANE:81:plane 2C] fb: [NOFB], visible: no
  • <7> [377.680797] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [PLANE:89:cursor C] fb: [NOFB], visible: no
  • <7> [377.681015] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:94:DDI A/PHY A]
  • <7> [377.681069] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:102:DDI B/PHY B]
  • <7> [377.681122] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:104:DP-MST A]
  • <7> [377.681174] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:105:DP-MST B]
  • <7> [377.681227] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:106:DP-MST C]
  • <7> [377.681280] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:113:DDI C/PHY C]
  • <7> [377.681332] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:115:DP-MST A]
  • <7> [377.681384] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:116:DP-MST B]
  • <7> [377.681436] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:117:DP-MST C]
  • <7> [377.681487] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.141 [i915]] DPLL 0
  • <7> [377.681551] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.141 [i915]] DPLL 1
  • <7> [377.681642] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.141 [i915]] DPLL 2
  • <7> [377.681703] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.141 [i915]] DPLL 3
  • <7> [377.681745] i915 0000:00:02.0: [drm:intel_sagv_pre_plane_update [i915]] Disabling SAGV
  • <7> [377.689464] i915 0000:00:02.0: [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 51
  • <7> [377.689540] i915 0000:00:02.0: [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
  • <7> [377.689662] i915 0000:00:02.0: [drm:edp_panel_on [i915]] Turn [ENCODER:94:DDI A/PHY A] panel power on
  • <7> [377.689761] i915 0000:00:02.0: [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
  • <7> [377.689960] i915 0000:00:02.0: [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
  • <7> [377.690058] i915 0000:00:02.0: [drm:wait_panel_status [i915]] Wait complete
  • <7> [377.690204] i915 0000:00:02.0: [drm:edp_panel_on [i915]] Wait for panel power on
  • <7> [377.690401] i915 0000:00:02.0: [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
  • <7> [377.725435] i915 0000:00:02.0: [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12001010, pins 0x00000010, long 0x00000010
  • <7> [377.725514] i915 0000:00:02.0: [drm:intel_hpd_irq_handler [i915]] digital hpd on [ENCODER:94:DDI A/PHY A] - long
  • <7> [377.725590] i915 0000:00:02.0: [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 10
  • <7> [377.725675] i915 0000:00:02.0: [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP [ENCODER:94:DDI A/PHY A]
  • <7> [377.899697] i915 0000:00:02.0: [drm:wait_panel_status [i915]] Wait complete
  • <7> [377.899766] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
  • <7> [377.899899] i915 0000:00:02.0: [drm:edp_panel_vdd_on [i915]] Turning [ENCODER:94:DDI A/PHY A] VDD on
  • <7> [377.900105] i915 0000:00:02.0: [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
  • <7> [377.901443] i915 0000:00:02.0: [drm:intel_dp_start_link_train [i915]] Using LINK_RATE_SET value 07
  • <7> [377.902261] i915 0000:00:02.0: [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
  • <7> [377.902310] i915 0000:00:02.0: [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
  • <7> [377.902359] i915 0000:00:02.0: [drm:hsw_set_signal_levels [i915]] Using signal levels 00000000
  • <7> [377.902413] i915 0000:00:02.0: [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
  • <7> [377.903460] i915 0000:00:02.0: [drm:intel_dp_link_train_phy [i915]] clock recovery OK
  • <7> [377.903509] i915 0000:00:02.0: [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
  • <7> [377.905147] i915 0000:00:02.0: [drm:intel_dp_link_train_phy [i915]] Channel EQ done. DP Training successful
  • <7> [377.905199] i915 0000:00:02.0: [drm:intel_dp_link_train_phy [i915]] [CONNECTOR:95:eDP-1] Link Training passed at link rate = 540000, lane count = 2, at DPRX
  • <7> [377.905538] i915 0000:00:02.0: [drm:intel_enable_pipe [i915]] enabling pipe A
  • <7> [377.905647] i915 0000:00:02.0: [drm:intel_edp_backlight_on [i915]]
  • <7> [377.905697] i915 0000:00:02.0: [drm:intel_panel_enable_backlight [i915]] pipe A
  • <7> [377.905826] i915 0000:00:02.0: [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
  • <7> [377.906088] i915 0000:00:02.0: [drm:intel_psr_enable_locked [i915]] Enabling PSR2
  • <7> [377.906956] i915 0000:00:02.0: [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 6, on? 1) for crtc 93
  • <7> [377.907027] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
  • <7> [377.907784] i915 0000:00:02.0: [drm:intel_dp_lttpr_init [i915]] LTTPR common capabilities: 00 00 00 00 00 00 00 00
  • <7> [377.933779] [drm:drm_dp_dpcd_access] AUX C/DDI C/PHY C: Too many retries, giving up. First error: -5
  • <7> [377.934651] i915 0000:00:02.0: [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 06
  • <7> [377.935292] i915 0000:00:02.0: [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
  • <7> [377.935360] i915 0000:00:02.0: [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
  • <7> [377.935426] i915 0000:00:02.0: [drm:hsw_set_signal_levels [i915]] Using signal levels 00000000
  • <7> [377.935498] i915 0000:00:02.0: [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
  • <7> [377.936438] i915 0000:00:02.0: [drm:intel_dp_link_train_phy [i915]] clock recovery OK
  • <7> [377.936493] i915 0000:00:02.0: [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
  • <7> [377.938075] i915 0000:00:02.0: [drm:intel_dp_link_train_phy [i915]] Channel EQ done. DP Training successful
  • <7> [377.938131] i915 0000:00:02.0: [drm:intel_dp_link_train_phy [i915]] [CONNECTOR:114:DP-2] Link Training passed at link rate = 162000, lane count = 4, at DPRX
  • <7> [377.938801] i915 0000:00:02.0: [drm:intel_enable_pipe [i915]] enabling pipe C
  • <7> [377.938927] i915 0000:00:02.0: [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:114:DP-2], [ENCODER:113:DDI C/PHY C]
  • <7> [377.938983] i915 0000:00:02.0: [drm:hsw_audio_codec_enable [i915]] Enable audio codec on transcoder C, 32 bytes ELD
  • <7> [377.939071] i915 0000:00:02.0: [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
  • <7> [377.939213] i915 0000:00:02.0: [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
  • <7> [377.939294] i915 0000:00:02.0: [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
  • <7> [377.953935] i915 0000:00:02.0: [drm:i915_audio_component_get_power [i915]] restored AUD_FREQ_CNTRL to 0x10
  • <7> [377.955881] i915 0000:00:02.0: [drm:verify_connector_state [i915]] [CONNECTOR:95:eDP-1]
  • <7> [377.955970] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [CRTC:51:pipe A]
  • <7> [377.956127] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.141 [i915]] DPLL 0
  • <7> [377.956271] i915 0000:00:02.0: [drm:verify_connector_state [i915]] [CONNECTOR:114:DP-2]
  • <7> [377.956368] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [CRTC:93:pipe C]
  • <7> [377.956539] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.141 [i915]] DPLL 1
To upload designs, you'll need to enable LFS and have an admin enable hashed storage. More information