few tests - dmesg-warn - *ERROR* CPU pipe * FIFO underrun
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143600v1/bat-apl-1/igt@kms_busy@basic.html
<7> [169.007436] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] [PLANE:48:plane 3A] fb: [NOFB], visible: no
<7> [169.008116] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] [PLANE:56:cursor A] fb: [NOFB], visible: no
<7> [169.071313] i915 0000:00:02.0: [drm:intel_audio_codec_disable [i915]] [CONNECTOR:115:DP-1][ENCODER:114:DDI B/PHY B] Disable audio codec on [CRTC:61:pipe A]
<7> [169.106506] i915 0000:00:02.0: [drm:intel_audio_component_get_eld [i915]] Not valid for port B
<3> [169.106923] i915 0000:00:02.0: [drm] *ERROR* CPU pipe A FIFO underrun
<7> [169.107165] i915 0000:00:02.0: [drm:intel_fbc_underrun_work_fn [i915]] Disabling FBC due to FIFO underrun.
<7> [169.125969] i915 0000:00:02.0: [drm:__intel_fbc_disable [i915]] Disabling FBC on [PLANE:32:plane 1A]
<7> [169.130243] i915 0000:00:02.0: [drm:intel_disable_transcoder [i915]] disabling pipe A
<7> [169.142806] i915 0000:00:02.0: [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 0x1, on? 1) for [CRTC:61:pipe A]
<7> [169.144369] i915 0000:00:02.0: [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
<7> [169.145095] i915 0000:00:02.0: [drm:intel_set_cdclk [i915]] Pre changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz, bypass 19200 kHz, voltage level 6
<7> [169.146648] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:114:DDI B/PHY B]
<7> [169.147402] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:116:DP-MST A]