<6> [337.486466] [IGT] kms_pipe_crc_basic: starting subtest suspend-read-crc-pipe-B
<7> [337.486985] [drm:drm_mode_addfb2] [FB:267]
<7> [337.548865] [drm:drm_mode_setcrtc] [CRTC:91:pipe A]
<7> [337.549083] i915 0000:00:02.0: [drm:intel_modeset_calc_cdclk [i915]] New cdclk calculated to be logical 172800 kHz, actual 172800 kHz
<7> [337.549151] i915 0000:00:02.0: [drm:intel_modeset_calc_cdclk [i915]] New voltage level calculated to be logical 0, actual 0
<7> [337.549244] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] ddb ( 0 - 992) -> ( 0 - 0), size 992 -> 0
<7> [337.549283] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:87:cursor A] ddb ( 992 - 1024) -> ( 0 - 0), size 32 -> 0
<7> [337.549321] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7,*twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm
<7> [337.549359] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] lines 1, 2, 2, 2, 3, 6, 7, 8, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0
<7> [337.549398] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] blocks 9, 33, 33, 33, 49, 97, 113, 129, 23 -> 0, 0, 0, 0, 0, 0, 0, 0, 0
<7> [337.549441] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] min_ddb 11, 38, 38, 38, 55, 108, 126, 143, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0
<7> [337.549526] i915 0000:00:02.0: [drm:intel_bw_atomic_check [i915]] pipe A data rate 0 num active planes 0
<7> [337.549655] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [CRTC:91:pipe A] enable: no [modeset]
<7> [337.549728] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 1A] fb: [NOFB], visible: no
<7> [337.549792] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 2A] fb: [NOFB], visible: no
<7> [337.549852] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [PLANE:47:plane 3A] fb: [NOFB], visible: no
<7> [337.549914] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [PLANE:55:plane 4A] fb: [NOFB], visible: no
<7> [337.549973] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [PLANE:63:plane 5A] fb: [NOFB], visible: no
<7> [337.550031] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [PLANE:71:plane 6A] fb: [NOFB], visible: no
<7> [337.550090] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [PLANE:79:plane 7A] fb: [NOFB], visible: no
<7> [337.550146] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [PLANE:87:cursor A] fb: [NOFB], visible: no
<7> [337.552656] i915 0000:00:02.0: [drm:intel_psr_disable_locked [i915]] Disabling PSR1
<7> [337.553015] [drm:intel_edp_backlight_off [i915]]
<7> [337.755868] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
<7> [337.756146] i915 0000:00:02.0: [drm:intel_disable_pipe [i915]] disabling pipe A
<7> [337.766026] i915 0000:00:02.0: [drm:intel_edp_panel_off.part.53 [i915]] Turn [ENCODER:214:DDI A] panel power off
<7> [337.766260] [drm:intel_edp_panel_off.part.53 [i915]] Wait for panel power off time
<7> [337.766561] i915 0000:00:02.0: [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
<7> [337.820553] i915 0000:00:02.0: [drm:wait_panel_status [i915]] Wait complete
<7> [337.820755] i915 0000:00:02.0: [drm:intel_power_well_disable [i915]] disabling DDI A IO
<7> [337.820908] i915 0000:00:02.0: [drm:intel_power_well_disable [i915]] disabling AUX A
<7> [337.821058] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
<7> [337.821189] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 91
<7> [337.821346] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
<7> [337.821494] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:214:DDI A]
<7> [337.821693] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:221:DDI B]
<7> [337.821818] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:223:DP-MST A]
<7> [337.821936] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:224:DP-MST B]
<7> [337.822057] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:225:DP-MST C]
<7> [337.822171] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:236:DDI C]
<7> [337.822286] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:238:DP-MST A]
<7> [337.822396] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:239:DP-MST B]
<7> [337.822542] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:240:DP-MST C]
<7> [337.822734] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:243:DDI D]
<7> [337.822855] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:245:DP-MST A]
<7> [337.822977] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:246:DP-MST B]
<7> [337.823056] i915 0000:00:02.0: [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x00010000, dig 0x0000008a, pins 0x00000010, long 0x00000010
<7> [337.823174] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:247:DP-MST C]
<7> [337.823324] [drm:intel_hpd_irq_handler [i915]] digital hpd on [ENCODER:214:DDI A] - long
<7> [337.823440] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:250:DDI E]
<7> [337.823577] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 10
<7> [337.823728] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:252:DP-MST A]
<7> [337.823884] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP [ENCODER:214:DDI A]
<7> [337.823991] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:253:DP-MST B]
<7> [337.824095] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:254:DP-MST C]
<7> [337.824198] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:257:DDI F]
<7> [337.824303] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:259:DP-MST A]
<7> [337.824429] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:260:DP-MST B]
<7> [337.824537] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:261:DP-MST C]
<7> [337.824663] i915 0000:00:02.0: [drm:verify_connector_state [i915]] [CONNECTOR:215:eDP-1]
<7> [337.824826] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.150 [i915]] DPLL 0
<7> [337.824963] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.150 [i915]] DPLL 1
<7> [337.825095] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.150 [i915]] TBT PLL
<7> [337.825225] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.150 [i915]] MG PLL 1
<7> [337.825360] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.150 [i915]] MG PLL 2
<7> [337.825487] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.150 [i915]] MG PLL 3
<7> [337.825650] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.150 [i915]] MG PLL 4
<7> [337.825842] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [CRTC:91:pipe A]
<7> [337.826122] i915 0000:00:02.0: [drm:intel_power_well_disable [i915]] disabling DC off
<7> [337.826264] i915 0000:00:02.0: [drm:skl_enable_dc6 [i915]] Enabling DC6
<7> [337.826390] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
<7> [337.827355] i915 0000:00:02.0: [drm:intel_power_well_disable [i915]] disabling always-on
<7> [337.827718] i915 Wakeref last acquired:
track_intel_runtime_pm_wakeref+0x14/0x90 [i915]
vm_fault_gtt+0x107/0x990 [i915]
__do_fault+0x45/0xfd
__handle_mm_fault+0xaf8/0x11d0
handle_mm_fault+0x154/0x350
__do_page_fault+0x2bb/0x4f0
page_fault+0x34/0x40
<7> [337.828373] i915 Wakeref last released:
__untrack_all_wakerefs+0x67/0x70 [i915]
__intel_wakeref_dec_and_check_tracking+0x61/0x80 [i915]
__intel_runtime_pm_put+0x106/0x270 [i915]
i915_gem_object_release_mmap+0x58/0x70 [i915]
i915_gem_object_set_tiling+0x174/0x770 [i915]
i915_gem_set_tiling_ioctl+0x1b2/0x310 [i915]
drm_ioctl_kernel+0xad/0xf0
drm_ioctl+0x2e1/0x390
<7> [337.828380] i915 Wakeref count: 7
<7> [337.828986] i915 Wakeref x4 taken at:
track_intel_runtime_pm_wakeref+0x14/0x90 [i915]
intel_display_power_get+0x1f/0x60 [i915]
modeset_get_crtc_power_domains+0x123/0x140 [i915]
intel_atomic_commit_tail+0xd4/0x1480 [i915]
intel_atomic_commit+0x312/0x390 [i915]
drm_atomic_helper_set_config+0x57/0xa0
drm_mode_setcrtc+0x1be/0x710
drm_ioctl_kernel+0xad/0xf0
<7> [337.830003] i915 Wakeref x1 taken at:
track_intel_runtime_pm_wakeref+0x14/0x90 [i915]
intel_display_power_get+0x1f/0x60 [i915]
intel_ddi_pre_pll_enable+0x6e/0x120 [i915]
intel_encoders_pre_pll_enable+0x76/0x90 [i915]
hsw_crtc_enable+0x67/0x580 [i915]
intel_update_crtc+0x1aa/0x1d0 [i915]
skl_commit_modeset_enables+0x5a3/0x600 [i915]
intel_atomic_commit_tail+0x30d/0x1480 [i915]
<7> [337.830957] i915 Wakeref x1 taken at:
track_intel_runtime_pm_wakeref+0x14/0x90 [i915]
intel_display_power_get+0x1f/0x60 [i915]
intel_ddi_pre_enable+0x1bf/0xd60 [i915]
intel_encoders_pre_enable+0x76/0x90 [i915]
hsw_crtc_enable+0x88/0x580 [i915]
intel_update_crtc+0x1aa/0x1d0 [i915]
skl_commit_modeset_enables+0x5a3/0x600 [i915]
intel_atomic_commit_tail+0x30d/0x1480 [i915]
<7> [337.831647] i915 Wakeref x1 taken at:
track_intel_runtime_pm_wakeref+0x14/0x90 [i915]
intel_display_power_get+0x1f/0x60 [i915]
edp_panel_vdd_on+0xd5/0x220 [i915]
intel_dp_aux_xfer+0xeb/0x960 [i915]
intel_dp_aux_transfer+0x124/0x200 [i915]
drm_dp_dpcd_access+0x76/0x110
drm_dp_dpcd_write+0x2a/0xb0
intel_dp_sink_dpms+0x4f/0x100 [i915]
<7> [337.839385] [drm:drm_mode_setcrtc] [CRTC:152:pipe B]
<7> [337.839426] [drm:drm_mode_setcrtc] [CONNECTOR:215:eDP-1]
<7> [337.839628] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CONNECTOR:215:eDP-1] Limiting display bpp to 24 instead of EDID bpp 24, requested bpp 36, max platform bpp 36
<7> [337.839715] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max rate 270000 max bpp 24 pixel clock 138780KHz
<7> [337.839789] [drm:intel_dp_compute_config [i915]] Force DSC en = 0
<7> [337.839861] [drm:intel_dp_compute_config [i915]] DP lane count 2 clock 270000 bpp 24
<7> [337.839934] [drm:intel_dp_compute_config [i915]] DP link rate required 416340 available 540000
<7> [337.840017] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] hw max bpp: 24, pipe bpp: 24, dithering: 0
<7> [337.840076] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:152:pipe B] fastset mismatch in cpu_transcoder (expected -1, found 4)
<7> [337.840127] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:152:pipe B] fastset mismatch in lane_count (expected 0, found 2)
<7> [337.840176] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:152:pipe B] fastset mismatch in dp_m_n (expected tu 0 gmch 0/0 link 0/0, or tu 0 gmch 0/0 link 0/0, found tu 64, gmch 6467616/8388608 link 269484/524288)
<7> [337.840225] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:152:pipe B] fastset mismatch in output_types (expected 0x00000000, found 0x00000100)
<7> [337.840279] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:152:pipe B] fastset mismatch in hw.adjusted_mode.crtc_hdisplay (expected 0, found 1920)
<7> [337.840343] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:152:pipe B] fastset mismatch in hw.adjusted_mode.crtc_htotal (expected 0, found 2080)
<7> [337.840409] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:152:pipe B] fastset mismatch in hw.adjusted_mode.crtc_hblank_start (expected 0, found 1920)
<7> [337.840472] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:152:pipe B] fastset mismatch in hw.adjusted_mode.crtc_hblank_end (expected 0, found 2080)
<7> [337.840527] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:152:pipe B] fastset mismatch in hw.adjusted_mode.crtc_hsync_start (expected 0, found 1966)
<7> [337.840601] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:152:pipe B] fastset mismatch in hw.adjusted_mode.crtc_hsync_end (expected 0, found 1996)
<7> [337.840652] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:152:pipe B] fastset mismatch in hw.adjusted_mode.crtc_vdisplay (expected 0, found 1080)
<7> [337.840702] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:152:pipe B] fastset mismatch in hw.adjusted_mode.crtc_vtotal (expected 0, found 1112)
<7> [337.840751] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:152:pipe B] fastset mismatch in hw.adjusted_mode.crtc_vblank_start (expected 0, found 1080)
<7> [337.840799] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:152:pipe B] fastset mismatch in hw.adjusted_mode.crtc_vblank_end (expected 0, found 1112)
<7> [337.840847] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:152:pipe B] fastset mismatch in hw.adjusted_mode.crtc_vsync_start (expected 0, found 1082)
<7> [337.840896] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:152:pipe B] fastset mismatch in hw.adjusted_mode.crtc_vsync_end (expected 0, found 1086)
<7> [337.840943] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:152:pipe B] fastset mismatch in pixel_multiplier (expected 0, found 1)
<7> [337.840990] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:152:pipe B] fastset mismatch in output_format (expected 0, found 1)
<7> [337.841036] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:152:pipe B] fastset mismatch in hw.adjusted_mode.flags (2) (expected 0, found 2)
<7> [337.841082] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:152:pipe B] fastset mismatch in hw.adjusted_mode.flags (8) (expected 0, found 8)
<7> [337.841130] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:152:pipe B] fastset mismatch in pipe_bpp (expected 0, found 24)
<7> [337.841179] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:152:pipe B] fastset mismatch in hw.adjusted_mode.crtc_clock (expected 0, found 138780)
<7> [337.841227] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:152:pipe B] fastset mismatch in port_clock (expected 0, found 270000)
<7> [337.841301] i915 0000:00:02.0: [drm:intel_plane_calc_min_cdclk [i915]] [PLANE:92:plane 1B] min cdclk (69390 kHz) > [CRTC:152:pipe B] min cdclk (0 kHz)
<7> [337.841360] i915 0000:00:02.0: [drm:intel_modeset_calc_cdclk [i915]] New cdclk calculated to be logical 172800 kHz, actual 172800 kHz
<7> [337.841429] i915 0000:00:02.0: [drm:intel_modeset_calc_cdclk [i915]] New voltage level calculated to be logical 0, actual 0
<7> [337.841500] [drm:intel_find_shared_dpll [i915]] [CRTC:152:pipe B] allocated DPLL 0
<7> [337.841588] [drm:intel_reference_shared_dpll.isra.12 [i915]] using DPLL 0 for pipe B
<7> [337.841669] [drm:skl_allocate_pipe_ddb [i915]] DBuf slice mask 1 pipe B active pipes 2
<7> [337.841705] [drm:skl_allocate_pipe_ddb [i915]] Pipe 1 ddb 0-1024
<7> [337.841735] [drm:skl_allocate_pipe_ddb [i915]] Enabled ddb slices mask 1 num supported 2
<7> [337.841770] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:92:plane 1B] ddb ( 0 - 0) -> ( 0 - 992), size 0 -> 992
<7> [337.841801] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:148:cursor B] ddb ( 0 - 0) -> ( 992 - 1024), size 0 -> 32
<7> [337.841833] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:92:plane 1B] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7,*twm
<7> [337.841865] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:92:plane 1B] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 1, 2, 2, 2, 3, 6, 7, 8, 0
<7> [337.841896] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:92:plane 1B] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 9, 33, 33, 33, 49, 97, 113, 129, 23
<7> [337.841926] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:92:plane 1B] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 38, 38, 38, 55, 108, 126, 143, 0
<7> [337.841991] i915 0000:00:02.0: [drm:intel_bw_atomic_check [i915]] pipe B data rate 555120 num active planes 1
<7> [337.842042] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [CRTC:152:pipe B] enable: yes [modeset]
<7> [337.842093] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] active: yes, output_types: EDP (0x100), output format: RGB
<7> [337.842142] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
<7> [337.842191] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
<7> [337.842240] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] dp m2_n2: lanes: 2; gmch_m: 4311744, gmch_n: 8388608, link_m: 179656, link_n: 524288, tu: 64
<7> [337.842287] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0, infoframes enabled: 0x0
<7> [337.842339] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] requested mode:
<7> [337.842344] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
<7> [337.842390] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] adjusted mode:
<7> [337.842393] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
<7> [337.842443] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
<7> [337.842509] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
<7> [337.842600] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] linetime: 120, ips linetime: 0
<7> [337.842661] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
<7> [337.842711] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled, force thru: no
<7> [337.842766] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
<7> [337.842817] [drm:icl_dump_hw_state [i915]] dpll_hw_state: cfgcr0: 0x1c001a5, cfgcr1: 0x8b, mg_refclkin_ctl: 0x0, hg_clktop2_coreclkctl1: 0x0, mg_clktop2_hsclkctl: 0x0, mg_pll_div0: 0x0, mg_pll_div2: 0x0, mg_pll_lf: 0x0, mg_pll_frac_lock: 0x0, mg_pll_ssc: 0x0, mg_pll_bias: 0x0, mg_pll_tdc_coldst_bias: 0x0
<7> [337.842866] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] csc_mode: 0x0 gamma_mode: 0x0 gamma_enable: 0 csc_enable: 0
<7> [337.842914] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] MST master transcoder: <invalid>
<7> [337.842963] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [PLANE:92:plane 1B] fb: [FB:267] 1920x1080 format = XR24 little-endian (0x34325258), visible: yes
<7> [337.843010] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] rotation: 0x1, scaler: -1
<7> [337.843075] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] src: 1920.000000x1080.000000+0.000000+0.000000 dst: 1920x1080+0+0
<7> [337.843108] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [PLANE:100:plane 2B] fb: [NOFB], visible: no
<7> [337.843143] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [PLANE:108:plane 3B] fb: [NOFB], visible: no
<7> [337.843176] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [PLANE:116:plane 4B] fb: [NOFB], visible: no
<7> [337.843210] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [PLANE:124:plane 5B] fb: [NOFB], visible: no
<7> [337.843243] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [PLANE:132:plane 6B] fb: [NOFB], visible: no
<7> [337.843275] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [PLANE:140:plane 7B] fb: [NOFB], visible: no
<7> [337.843308] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [PLANE:148:cursor B] fb: [NOFB], visible: no
<7> [337.843908] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling always-on
<7> [337.843952] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling DC off
<7> [337.844385] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
<7> [337.844465] [drm:intel_combo_phy_init [i915]] Combo PHY A already enabled, won't reprogram it.
<7> [337.844550] [drm:intel_combo_phy_init [i915]] Combo PHY B already enabled, won't reprogram it.
<7> [337.844595] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling power well 2
<7> [337.844640] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling power well 3
<7> [337.844709] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:214:DDI A]
<7> [337.844745] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:221:DDI B]
<7> [337.844785] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:223:DP-MST A]
<7> [337.844832] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:224:DP-MST B]
<7> [337.844879] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:225:DP-MST C]
<7> [337.844927] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:236:DDI C]
<7> [337.844965] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:238:DP-MST A]
<7> [337.844999] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:239:DP-MST B]
<7> [337.845039] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:240:DP-MST C]
<7> [337.845075] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:243:DDI D]
<7> [337.845111] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:245:DP-MST A]
<7> [337.845147] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:246:DP-MST B]
<7> [337.845183] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:247:DP-MST C]
<7> [337.845218] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:250:DDI E]
<7> [337.845252] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:252:DP-MST A]
<7> [337.845291] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:253:DP-MST B]
<7> [337.845325] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:254:DP-MST C]
<7> [337.845359] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:257:DDI F]
<7> [337.845392] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:259:DP-MST A]
<7> [337.845424] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:260:DP-MST B]
<7> [337.845456] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:261:DP-MST C]
<7> [337.845493] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.150 [i915]] DPLL 0
<7> [337.845556] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.150 [i915]] DPLL 1
<7> [337.845598] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.150 [i915]] TBT PLL
<7> [337.845638] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.150 [i915]] MG PLL 1
<7> [337.845678] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.150 [i915]] MG PLL 2
<7> [337.845720] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.150 [i915]] MG PLL 3
<7> [337.845772] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.150 [i915]] MG PLL 4
<7> [337.845835] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling AUX A
<7> [337.845890] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 2, on? 0) for crtc 152
<7> [337.845925] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
<7> [337.846071] i915 0000:00:02.0: [drm:edp_panel_on [i915]] Turn [ENCODER:214:DDI A] panel power on
<7> [337.846123] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
<7> [338.428074] i915 0000:00:02.0: [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
<7> [338.443854] i915 0000:00:02.0: [drm:wait_panel_status [i915]] Wait complete
<7> [338.444116] [drm:edp_panel_on [i915]] Wait for panel power on
<7> [338.444427] i915 0000:00:02.0: [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
<7> [338.477564] i915 0000:00:02.0: [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x00010000, dig 0x0000008a, pins 0x00000010, long 0x00000010
<7> [338.477710] [drm:intel_hpd_irq_handler [i915]] digital hpd on [ENCODER:214:DDI A] - long
<7> [338.477846] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 20
<7> [338.478146] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP [ENCODER:214:DDI A]
<7> [338.654894] i915 0000:00:02.0: [drm:wait_panel_status [i915]] Wait complete
<7> [338.655085] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling DDI A IO
<7> [338.655525] i915 0000:00:02.0: [drm:edp_panel_vdd_on [i915]] Turning [ENCODER:214:DDI A] VDD on
<7> [338.656082] i915 0000:00:02.0: [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
<7> [338.657339] [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a
<7> [338.658470] i915 0000:00:02.0: [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
<7> [338.658705] i915 0000:00:02.0: [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
<7> [338.658883] i915 0000:00:02.0: [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
<7> [338.660387] [drm:intel_dp_start_link_train [i915]] clock recovery OK
<7> [338.660539] i915 0000:00:02.0: [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
<7> [338.663618] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
<7> [338.663802] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:215:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
<7> [338.664422] i915 0000:00:02.0: [drm:intel_enable_pipe [i915]] enabling pipe B
<7> [338.664881] [drm:intel_edp_backlight_on [i915]]
<7> [338.665027] i915 0000:00:02.0: [drm:intel_panel_enable_backlight [i915]] pipe B
<7> [338.665236] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
<7> [338.665667] i915 0000:00:02.0: [drm:intel_psr_enable_locked [i915]] Enabling PSR1
<7> [338.666700] i915 0000:00:02.0: [drm:intel_enable_ddi [i915]] PSR enabled. Not enabling DRRS.
<7> [338.681837] i915 0000:00:02.0: [drm:verify_connector_state [i915]] [CONNECTOR:215:eDP-1]
<7> [338.681924] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [CRTC:152:pipe B]
<7> [338.682106] [drm:intel_ddi_get_config [i915]] [ENCODER:214:DDI A] Fec status: 0
<7> [338.682144] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.150 [i915]] DPLL 0
<7> [338.685171] [drm:drm_mode_setcrtc] [CRTC:213:pipe C]
<7> [338.699074] i915 0000:00:02.0: [drm:i915_fifo_underrun_reset_write [i915]] Re-arming FIFO underruns on pipe B
<7> [338.699215] i915 0000:00:02.0: [drm:i915_fifo_underrun_reset_write [i915]] Re-arming FIFO underruns on pipe B
<7> [338.699347] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CONNECTOR:215:eDP-1] Limiting display bpp to 24 instead of EDID bpp 24, requested bpp 36, max platform bpp 36
<7> [338.699392] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max rate 270000 max bpp 24 pixel clock 138780KHz
<7> [338.699428] [drm:intel_dp_compute_config [i915]] Force DSC en = 0
<7> [338.699462] [drm:intel_dp_compute_config [i915]] DP lane count 2 clock 270000 bpp 24
<7> [338.699500] [drm:intel_dp_compute_config [i915]] DP link rate required 416340 available 540000
<7> [338.699611] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] hw max bpp: 24, pipe bpp: 24, dithering: 0
<7> [338.699675] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [CRTC:152:pipe B] enable: yes [fastset]
<7> [338.699781] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] active: yes, output_types: EDP (0x100), output format: RGB
<7> [338.699827] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
<7> [338.699867] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
<7> [338.699903] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] dp m2_n2: lanes: 2; gmch_m: 4311744, gmch_n: 8388608, link_m: 179656, link_n: 524288, tu: 64
<7> [338.699963] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0, infoframes enabled: 0x0
<7> [338.699998] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] requested mode:
<7> [338.700034] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
<7> [338.700069] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] adjusted mode:
<7> [338.700071] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
<7> [338.700105] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
<7> [338.700138] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
<7> [338.700172] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] linetime: 120, ips linetime: 0
<7> [338.700207] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
<7> [338.700267] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled, force thru: no
<7> [338.700300] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
<7> [338.700333] [drm:icl_dump_hw_state [i915]] dpll_hw_state: cfgcr0: 0x1c001a5, cfgcr1: 0x8b, mg_refclkin_ctl: 0x0, hg_clktop2_coreclkctl1: 0x0, mg_clktop2_hsclkctl: 0x0, mg_pll_div0: 0x0, mg_pll_div2: 0x0, mg_pll_lf: 0x0, mg_pll_frac_lock: 0x0, mg_pll_ssc: 0x0, mg_pll_bias: 0x0, mg_pll_tdc_coldst_bias: 0x0
<7> [338.700395] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] csc_mode: 0x0 gamma_mode: 0x0 gamma_enable: 0 csc_enable: 0
<7> [338.700429] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] MST master transcoder: <invalid>
<7> [338.700464] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [PLANE:92:plane 1B] fb: [FB:267] 1920x1080 format = XR24 little-endian (0x34325258), visible: yes
<7> [338.700507] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] rotation: 0x1, scaler: -1
<7> [338.700580] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] src: 1920.000000x1080.000000+0.000000+0.000000 dst: 1920x1080+0+0
<7> [338.700699] i915 0000:00:02.0: [drm:intel_ddi_update_pipe [i915]] PSR enabled. Not enabling DRRS.
<7> [338.714957] i915 0000:00:02.0: [drm:verify_connector_state [i915]] [CONNECTOR:215:eDP-1]
<7> [338.715011] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [CRTC:152:pipe B]
<7> [338.715207] [drm:intel_ddi_get_config [i915]] [ENCODER:214:DDI A] Fec status: 0
<7> [338.715247] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.150 [i915]] DPLL 0
<7> [338.798911] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CONNECTOR:215:eDP-1] Limiting display bpp to 24 instead of EDID bpp 24, requested bpp 36, max platform bpp 36
<7> [338.799052] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max rate 270000 max bpp 24 pixel clock 138780KHz
<7> [338.799165] [drm:intel_dp_compute_config [i915]] Force DSC en = 0
<7> [338.799277] [drm:intel_dp_compute_config [i915]] DP lane count 2 clock 270000 bpp 24
<7> [338.799385] [drm:intel_dp_compute_config [i915]] DP link rate required 416340 available 540000
<7> [338.799497] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] hw max bpp: 24, pipe bpp: 24, dithering: 0
<7> [338.799776] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [CRTC:152:pipe B] enable: yes [fastset]
<7> [338.799931] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] active: yes, output_types: EDP (0x100), output format: RGB
<7> [338.800073] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
<7> [338.800207] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
<7> [338.800318] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] dp m2_n2: lanes: 2; gmch_m: 4311744, gmch_n: 8388608, link_m: 179656, link_n: 524288, tu: 64
<7> [338.800452] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0, infoframes enabled: 0x0
<7> [338.800583] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] requested mode:
<7> [338.800625] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
<7> [338.800731] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] adjusted mode:
<7> [338.800741] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
<7> [338.800848] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
<7> [338.800954] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
<7> [338.801059] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] linetime: 120, ips linetime: 0
<7> [338.801160] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
<7> [338.801260] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled, force thru: no
<7> [338.801361] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
<7> [338.801486] [drm:icl_dump_hw_state [i915]] dpll_hw_state: cfgcr0: 0x1c001a5, cfgcr1: 0x8b, mg_refclkin_ctl: 0x0, hg_clktop2_coreclkctl1: 0x0, mg_clktop2_hsclkctl: 0x0, mg_pll_div0: 0x0, mg_pll_div2: 0x0, mg_pll_lf: 0x0, mg_pll_frac_lock: 0x0, mg_pll_ssc: 0x0, mg_pll_bias: 0x0, mg_pll_tdc_coldst_bias: 0x0
<7> [338.801677] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] csc_mode: 0x0 gamma_mode: 0x0 gamma_enable: 0 csc_enable: 0
<7> [338.801831] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] MST master transcoder: <invalid>
<7> [338.801983] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [PLANE:92:plane 1B] fb: [FB:267] 1920x1080 format = XR24 little-endian (0x34325258), visible: yes
<7> [338.802097] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] rotation: 0x1, scaler: -1
<7> [338.802221] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] src: 1920.000000x1080.000000+0.000000+0.000000 dst: 1920x1080+0+0
<7> [338.802485] i915 0000:00:02.0: [drm:intel_ddi_update_pipe [i915]] PSR enabled. Not enabling DRRS.
<7> [338.815208] i915 0000:00:02.0: [drm:verify_connector_state [i915]] [CONNECTOR:215:eDP-1]
<7> [338.815326] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [CRTC:152:pipe B]
<7> [338.815767] [drm:intel_ddi_get_config [i915]] [ENCODER:214:DDI A] Fec status: 0
<7> [338.815878] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.150 [i915]] DPLL 0
<7> [338.816153] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:92:plane 1B] ddb ( 0 - 992) -> ( 0 - 0), size 992 -> 0
<7> [338.816196] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:92:plane 1B] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7,*twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm
<7> [338.816237] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:92:plane 1B] lines 1, 2, 2, 2, 3, 6, 7, 8, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0
<7> [338.816277] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:92:plane 1B] blocks 9, 33, 33, 33, 49, 97, 113, 129, 23 -> 0, 0, 0, 0, 0, 0, 0, 0, 0
<7> [338.816317] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:92:plane 1B] min_ddb 11, 38, 38, 38, 55, 108, 126, 143, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0
<7> [338.816399] i915 0000:00:02.0: [drm:intel_bw_atomic_check [i915]] pipe B data rate 0 num active planes 0
<7> [338.831789] [drm:drm_mode_addfb2] [FB:267]
<7> [338.837979] [drm:drm_mode_setcrtc] [CRTC:152:pipe B]
<7> [338.838009] [drm:drm_mode_setcrtc] [CONNECTOR:215:eDP-1]
<7> [338.838098] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:92:plane 1B] ddb ( 0 - 0) -> ( 0 - 992), size 0 -> 992
<7> [338.838124] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:92:plane 1B] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7,*twm
<7> [338.838148] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:92:plane 1B] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 1, 2, 2, 2, 3, 6, 7, 8, 0
<7> [338.838171] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:92:plane 1B] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 9, 33, 33, 33, 49, 97, 113, 129, 23
<7> [338.838194] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:92:plane 1B] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 38, 38, 38, 55, 108, 126, 143, 0
<7> [338.838250] i915 0000:00:02.0: [drm:intel_bw_atomic_check [i915]] pipe B data rate 555120 num active planes 1
<7> [338.848294] i915 0000:00:02.0: [drm:i915_fifo_underrun_reset_write [i915]] Re-arming FIFO underruns on pipe B
<7> [338.848455] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CONNECTOR:215:eDP-1] Limiting display bpp to 24 instead of EDID bpp 24, requested bpp 36, max platform bpp 36
<7> [338.848505] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max rate 270000 max bpp 24 pixel clock 138780KHz
<7> [338.848562] [drm:intel_dp_compute_config [i915]] Force DSC en = 0
<7> [338.848600] [drm:intel_dp_compute_config [i915]] DP lane count 2 clock 270000 bpp 24
<7> [338.848637] [drm:intel_dp_compute_config [i915]] DP link rate required 416340 available 540000
<7> [338.848681] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] hw max bpp: 24, pipe bpp: 24, dithering: 0
<7> [338.848769] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [CRTC:152:pipe B] enable: yes [fastset]
<7> [338.848813] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] active: yes, output_types: EDP (0x100), output format: RGB
<7> [338.848847] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
<7> [338.848882] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
<7> [338.848915] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] dp m2_n2: lanes: 2; gmch_m: 4311744, gmch_n: 8388608, link_m: 179656, link_n: 524288, tu: 64
<7> [338.848948] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0, infoframes enabled: 0x0
<7> [338.848981] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] requested mode:
<7> [338.848984] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
<7> [338.849015] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] adjusted mode:
<7> [338.849018] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
<7> [338.849077] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
<7> [338.849112] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
<7> [338.849149] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] linetime: 120, ips linetime: 0
<7> [338.849219] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
<7> [338.849263] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled, force thru: no
<7> [338.849303] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
<7> [338.849336] [drm:icl_dump_hw_state [i915]] dpll_hw_state: cfgcr0: 0x1c001a5, cfgcr1: 0x8b, mg_refclkin_ctl: 0x0, hg_clktop2_coreclkctl1: 0x0, mg_clktop2_hsclkctl: 0x0, mg_pll_div0: 0x0, mg_pll_div2: 0x0, mg_pll_lf: 0x0, mg_pll_frac_lock: 0x0, mg_pll_ssc: 0x0, mg_pll_bias: 0x0, mg_pll_tdc_coldst_bias: 0x0
<7> [338.849367] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] csc_mode: 0x0 gamma_mode: 0x0 gamma_enable: 0 csc_enable: 0
<7> [338.849399] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] MST master transcoder: <invalid>
<7> [338.849466] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [PLANE:92:plane 1B] fb: [FB:267] 1920x1080 format = XR24 little-endian (0x34325258), visible: yes
<7> [338.849512] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] rotation: 0x1, scaler: -1
<7> [338.849579] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] src: 1920.000000x1080.000000+0.000000+0.000000 dst: 1920x1080+0+0
<7> [338.849708] i915 0000:00:02.0: [drm:intel_ddi_update_pipe [i915]] PSR enabled. Not enabling DRRS.
<7> [338.864975] i915 0000:00:02.0: [drm:verify_connector_state [i915]] [CONNECTOR:215:eDP-1]
<7> [338.865029] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [CRTC:152:pipe B]
<7> [338.865224] [drm:intel_ddi_get_config [i915]] [ENCODER:214:DDI A] Fec status: 0
<7> [338.865265] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.150 [i915]] DPLL 0
<7> [338.948795] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CONNECTOR:215:eDP-1] Limiting display bpp to 24 instead of EDID bpp 24, requested bpp 36, max platform bpp 36
<7> [338.948915] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max rate 270000 max bpp 24 pixel clock 138780KHz
<7> [338.949011] [drm:intel_dp_compute_config [i915]] Force DSC en = 0
<7> [338.949105] [drm:intel_dp_compute_config [i915]] DP lane count 2 clock 270000 bpp 24
<7> [338.949196] [drm:intel_dp_compute_config [i915]] DP link rate required 416340 available 540000
<7> [338.949292] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] hw max bpp: 24, pipe bpp: 24, dithering: 0
<7> [338.949411] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [CRTC:152:pipe B] enable: yes [fastset]
<7> [338.949504] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] active: yes, output_types: EDP (0x100), output format: RGB
<7> [338.949648] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
<7> [338.949741] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
<7> [338.949858] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] dp m2_n2: lanes: 2; gmch_m: 4311744, gmch_n: 8388608, link_m: 179656, link_n: 524288, tu: 64
<7> [338.949956] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0, infoframes enabled: 0x0
<7> [338.950062] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] requested mode:
<7> [338.950075] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
<7> [338.950177] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] adjusted mode:
<7> [338.950187] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
<7> [338.950288] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
<7> [338.950387] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
<7> [338.950496] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] linetime: 120, ips linetime: 0
<7> [338.950669] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
<7> [338.950804] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled, force thru: no
<7> [338.950937] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
<7> [338.951060] [drm:icl_dump_hw_state [i915]] dpll_hw_state: cfgcr0: 0x1c001a5, cfgcr1: 0x8b, mg_refclkin_ctl: 0x0, hg_clktop2_coreclkctl1: 0x0, mg_clktop2_hsclkctl: 0x0, mg_pll_div0: 0x0, mg_pll_div2: 0x0, mg_pll_lf: 0x0, mg_pll_frac_lock: 0x0, mg_pll_ssc: 0x0, mg_pll_bias: 0x0, mg_pll_tdc_coldst_bias: 0x0
<7> [338.951155] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] csc_mode: 0x0 gamma_mode: 0x0 gamma_enable: 0 csc_enable: 0
<7> [338.951246] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] MST master transcoder: <invalid>
<7> [338.951341] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [PLANE:92:plane 1B] fb: [FB:267] 1920x1080 format = XR24 little-endian (0x34325258), visible: yes
<7> [338.951431] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] rotation: 0x1, scaler: -1
<7> [338.951531] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] src: 1920.000000x1080.000000+0.000000+0.000000 dst: 1920x1080+0+0
<7> [338.951882] i915 0000:00:02.0: [drm:intel_ddi_update_pipe [i915]] PSR enabled. Not enabling DRRS.
<7> [338.965093] i915 0000:00:02.0: [drm:verify_connector_state [i915]] [CONNECTOR:215:eDP-1]
<7> [338.965176] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [CRTC:152:pipe B]
<7> [338.965445] [drm:intel_ddi_get_config [i915]] [ENCODER:214:DDI A] Fec status: 0
<7> [338.965510] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.150 [i915]] DPLL 0
<7> [338.965836] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:92:plane 1B] ddb ( 0 - 992) -> ( 0 - 0), size 992 -> 0
<7> [338.965876] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:92:plane 1B] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7,*twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm
<7> [338.965914] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:92:plane 1B] lines 1, 2, 2, 2, 3, 6, 7, 8, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0
<7> [338.965950] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:92:plane 1B] blocks 9, 33, 33, 33, 49, 97, 113, 129, 23 -> 0, 0, 0, 0, 0, 0, 0, 0, 0
<7> [338.966010] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:92:plane 1B] min_ddb 11, 38, 38, 38, 55, 108, 126, 143, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0
<7> [338.966066] i915 0000:00:02.0: [drm:intel_bw_atomic_check [i915]] pipe B data rate 0 num active planes 0
<6> [339.044976] PM: suspend entry (s2idle)
<6> [339.051015] Filesystems sync: 0.006 seconds