VRR not available on DP 2.1

added DC VRR labels

@drago01 Just to confirm, when you validate DP1.4 VRR is working, are you using another DP1.4 VRR capable monitor, or using the Samsung DP2.1 monitor by forcing it light up at DP1.4 link rate ?

It's the same monitor, I am just switching the DP version in the OSD menu.

ok got you thanks.

@jzuo any updates on this one? With 6.8 I can use 7680x2160@240HZ just fine but when doing so all connectors are set to vrr_capable = 0.

@jzuo any news on this? Seems to be fine on windows so there should be something the driver can do about it.

mentioned in issue #3059

Hello! I’m having the same issue. Any news on this?

I am also seeing this issue on the same type of Samsung Odyssey G9 monitor with DisplayPort 2.1. I'm including some relevant logging from amd-staging-drm-next built from agd5f/linux@7be9027d of both the monitor's DisplayPort 1.4 VRR enabled edid-decode and drm_info as well as the DisplayPort 2.1 VRR missing edid-decode and drm_info in case it's helpful, along with a dmesg after toggling between monitor modes and DisplayPort revisions.

dmesg-dp1.4-dp2.1.log

drm_info-G95NC-240hz-dp1.4-vrr.txt

edid-G95NC-240hz-dp1.4-vrr.txt

drm_info-G95NC-240hz-dp2.1-novrr.txt

edid-G95NC-240hz-dp2.1-novrr.txt

There is no vrr_capable property attached for DP2.1 in the drm_info dump, which suggests this function (drm_connector_attach_vrr_capable_property) isn't called at all.

Both EDIDs should let VRR work (in your case max_vfreq - min_vfreq > 10, source).

Maybe you could hack the code so that the MST root check isn't there or simply register the property somewhere else and see if it gets set to 1 later?

Oh that's interesting. I am wondering why this is conditional on MST.

@jzuo do you know why this is?

Sorry for late reply. I've been occupied for weeks. Let me check why DP2 is mssing from vrr_capable property.

Since I am still in the middle of other tasks, please help to add below debug code, and let me know the debug print. (Need to add drm.debug=0x106 into grub). Thanks a lot.

amdgpu_dm_mst_types.c:
dm_dp_add_mst_connector() {
...
++   DRM_DEBUG_DRIVER("%s:%d MST_VRR drm_connector.vrr_capable_property=%p\n", __func__, __LINE__, master->base.vrr_capable_property);
     connector->vrr_capable_property = master->base.vrr_capable_property;
     if (connector->vrr_capable_property)
		drm_connector_attach_vrr_capable_property(connector);
...
}

amdgpu_dm.c:
amdgpu_dm_update_freesync_caps() {
...
          if (edid && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT || 
		     sink->sink_signal == SIGNAL_TYPE_EDP || 
++                   sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST)) {
               if (amdgpu_dm_connector->dc_link &&
		    amdgpu_dm_connector->dc_link->dpcd_caps.allow_invalid_MSA_timing_param) {
			if (edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ) {
				amdgpu_dm_connector->min_vfreq = connector->display_info.monitor_range.min_vfreq;
				amdgpu_dm_connector->max_vfreq = connector->display_info.monitor_range.max_vfreq;
				if (amdgpu_dm_connector->max_vfreq -
				    amdgpu_dm_connector->min_vfreq > 10)  {
++                   DRM_DEBUG_DRIVER("%s:%d MST_VRR freesync_capable --> true\n", __func__, __LINE__);
                                    freesync_capable = true; 
                                } 
			} else {
				edid_check_required = edid->version > 1 ||
						      (edid->version == 1 &&
						       edid->revision > 1);
			}
		}
...

                if (connector->vrr_capable_property) {
++                      DRM_DEBUG_DRIVER("%s:%d MST_VRR attach freesync_capable=%d to vrr property\n", __func__, __LINE__, freesync_capable);
                      drm_connector_set_vrr_capable_property(connector,
						       freesync_capable);
                }
}

@jzuo I did my best to manually rebase that onto amd-staging-drm-next since some of your diffs weren't lining up for me, and I'm only seeing one of those debugging logs in my dmesg so maybe I messed up:

debug-vrr.patch

drm_info_new.log

dmesg-new.log

@matte-schwartz Thanks for your debug log.

If you can add below's one line and catch the log one more that that would be great.

amdgpu_dm.c:
amdgpu_dm_update_freesync_caps() {
...
update:
	if (dm_con_state)
		dm_con_state->freesync_capable = freesync_capable;

	if (connector->state && amdgpu_dm_connector->dc_link && !freesync_capable &&
	    amdgpu_dm_connector->dc_link->replay_settings.config.replay_supported) {
		amdgpu_dm_connector->dc_link->replay_settings.config.replay_supported = false;
		amdgpu_dm_connector->dc_link->replay_settings.replay_feature_enabled = false;
	}

        if (connector->vrr_capable_property) {
++            DRM_DEBUG_DRIVER("%s:%d MST_VRR set freesync_capable=%d to vrr property\n", __func__, __LINE__, freesync_capable);
              drm_connector_set_vrr_capable_property(connector,
						       freesync_capable);
         }
}