- Jul 15, 2022
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Dylan Baker authored
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Dylan Baker authored
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- Jul 14, 2022
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Faith Ekstrand authored
Instead of trying to compact the surface state table to get rid of any unused render targets, emit MAX(1, colorAttachmentCount) surface states always. This ensures that secondaries will always match with primaries when we go to do the copy since there's no rule requiring the secondary to have VK_FORMAT_UNDEFINED when the primary has a NULL image view. Fixes: 3501a3f9 ("anv: Convert to 100% dynamic rendering") Part-of: <mesa/mesa!17013>
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Faith Ekstrand authored
The NULL path is dead because it can't actually be NULL. This cleans things up a bit. Part-of: <mesa/mesa!17013>
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- Jul 12, 2022
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Fixes arb_timer_query-timestamp-get on my radv system, where the GPU has been on for many days and the timestamp would only increment every once in a while. Part of fixing #6808 Fixes: 7a40b734 ("zink: handle timestamp queries") Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com> Part-of: <mesa/mesa!17477> (cherry picked from commit 0feedec9)
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cc: mesa-stable Reviewed-by: Dave Airlie <airlied@redhat.com> Part-of: <mesa/mesa!17469> (cherry picked from commit fb917a60)
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this clobbers pNext and breaks tooling, as found by Panagiotis Apostolou Fixes: f72d5a93 ("lavapipe: KHR_format_feature_flags2") Reviewed-by: Dave Airlie <airlied@redhat.com> Part-of: <mesa/mesa!17462> (cherry picked from commit 276557b9)
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Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: mesa-stable Reviewed-by: Nanley Chery <nanley.g.chery@intel.com> Part-of: <mesa/mesa!17329> (cherry picked from commit ab4beaf3)
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Make sure that the Operand is '1.0.xx'. Fixes: b03be30e ('aco: optimize packed fneg') Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Part-of: <mesa/mesa!17395> (cherry picked from commit 66d46a23)
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Fixes: a8c471f9 ('radv: gather more information about PS in the shader info pass') Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <mesa/mesa!17417> (cherry picked from commit 676700d6)
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This pass tries to move register usage closer to SSA, and for large shaders this means we can overflow the register index, which only has RC_REGISTER_INDEX_BITS size. This creates invalid code and leads to crash at a later stage. Limit the pool of available registers to RC_REGISTER_MAX_INDEX, currently is was two times the number of shader instructions. This means we'll fail the compile right away if we wanted more than RC_REGISTER_MAX_INDEX temps, but when we've got that many we're already well past how many instructions we can support anyway. CC: mesa-stable Closes: mesa/mesa#6017 Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com> Reviewed-by: Emma Anholt <emma@anholt.net> Part-of: <mesa/mesa!17393> (cherry picked from commit 42a3d22f)
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the EXT_external_object spec originally was underspecified with regards to this function, leaving room for synchronization errors where: * app calls SignalSemaphoreEXT to signal a semaphore * mesa defers pipe_context::fence_server_signal with threaded context * driver defers gpu submission * SignalSemaphoreEXT has long since returned, app submits vk cmdbuf waiting on semaphore * spec violation / device lost to prevent this, the spec is being changed to: 1) require an implicit flush when calling SignalSemaphoreEXT 2) require that this implicit flush also forces GPU submission before SignalSemaphoreEXT returns all affected drivers have been updated fixes #6568 cc: mesa-stable Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!17376> (cherry picked from commit 21b3a234)
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Fixes: b3b2f97f "radeonsi: add Wave32 heuristics and shader profiles" Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <mesa/mesa!17410> (cherry picked from commit 3b367001)
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The ray query status of a variable is tracked in the nir_variable::data. We need to store it in the serialization otherwise restoring NIR from a cache will drop the annotation. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes: 5a9cdab1 ("nir: track variables representing ray queries") Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <mesa/mesa!16059> (cherry picked from commit a4c5521e)
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The Vulkan specification states: > Query commands, for the same query and submitted to the same queue, > execute in their entirety in submission order, relative to each other. In > effect there is an implicit execution dependency from each such query > command to all query commands previously submitted to the same queue. Fixes dEQP-VK.query_pool.statistics_query.reset_after_copy.* Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Cc: mesa-stable Part-of: <mesa/mesa!17400> (cherry picked from commit 768cd571)
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Flushing the batch midframe (splitting a renderpass) is expensive on a tiler, as it requires the GPU to flush the framebuffer contents to main memory and read them back. Clearing the framebuffer should not trigger a flush. Apps expect clears to be (almost) free, flushing for a clear is at the very least unexpected behaviour. The only reason we previously flushed is to ensure we could always use a "fast" clear. But a slow clear is a heck of a lot faster than a flush ;-) Instead of flushing, we should clear with a draw (via u_blitter) in case a fast clear isn't possible. This fixes pathological performance for applications that rely on partial clears within a frame. This issue was identified with Inochi2D, which repeatedly clears the stencil buffer midframe, in order to implement masking efficiently with the stencil buffer. In total, the all-important workload of rendering Asahi Lina is improved from 17fps to 29fps on a panfrost device. Fixes: c138ca80 ("panfrost: Make sure a clear does not re-use a pre-existing batch") Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <mesa/mesa!17112> (cherry picked from commit 638b2235)
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With stages dispatching with a mask, we can run into situations where we don't have the global address in all lanes. The existing code always assumed we had the addres in at least lane0. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes: bb40e999 ("intel/nir: use a single intel intrinsic to deal with ray traversal") Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <mesa/mesa!17330> (cherry picked from commit 9680e0e4)
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Fixes: b5c390c1 ("vulkan/wsi: add support for detecting mit-shm pixmaps.") Reviewed-by: Jesse Natalie <jenatali@microsoft.com> Part-of: <mesa/mesa!17388> (cherry picked from commit 5abc05f1)
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Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Jesse Natalie <jenatali@microsoft.com> Part-of: <mesa/mesa!17388> (cherry picked from commit ca6bd57e)
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These opcodes where fixed to return an integer instead of a boolean value some time ago but the documentation for them was not updated and still talked about a boolean result. Fixes: b0d4ee52 ('nir/opcodes: Fix up uadd_carry and usub_borrow') Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com> Part-of: <mesa/mesa!17372> (cherry picked from commit 84a0dca9)
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Dylan Baker authored
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- Jul 06, 2022
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Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Cc: mesa-stable Part-of: <mesa/mesa!17001> (cherry picked from commit b91971c2)
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TGSI has no legitimate[1] notion of linked shaders, which means tgsi_to_nir should conservatively assume everything all shaders are separable. This requires setting nir->info.separate_shader to warn drivers that shader CSOs might be mixed and matched. Otherwise, the driver might enable optimizations that are invalid for separate shaders, causing issues when the shaders are later treated as separable. This will fix varying linking with u_blitter's shaders on Panfrost (Bifrost and older), when util_blitter_clear is used with Panfrost. [1] There was a TGSI property added recently to forward nir->info.separate_shader up to virglrenderer, but it's not actually used for anything in virglrenderer and I am still struggling to understand what the use case would be. My gut says we should revert b6340305 ("tgsi: Add SEPARABLE_PROGRAM property"), but I'm not interested in fighting that yak right now. Notably, the u_blitter and hud shaders are separable but are not marked with this property. Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Reviewed-by: Emma Anholt <emma@anholt.net> Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com> Cc: mesa-stable Part-of: <mesa/mesa!17282> (cherry picked from commit 151aa19c)
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Cc: mesa-stable Reviewed-by: Emma Anholt <emma@anholt.net> Part-of: <mesa/mesa!17276> (cherry picked from commit 862f1eac)
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Fixes VK_ERROR_OUT_OF_POOL_MEMORY in the inlineuniformblocks sample from Sascha Willems. Fixes: ea3223e7 ('v3dv: implement VK_EXT_inline_uniform_block') Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com> Part-of: <mesa/mesa!17311> (cherry picked from commit 7b91b39b)
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VUID-VkViewport-minDepth-01234 specifies that depth must be in the range [0.0, 1.0], so the viewport must always be clamped to this range this affects texture clears using u_blitter, as this expects to be able to use the GL range of [-1.0, 1.0], so pass the depth value as though it's been de-converted back to a GL z coordinate to account for viewport transform cc: mesa-stable fixes #6757 Reviewed-by: Dave Airlie <airlied@redhat.com> Part-of: <mesa/mesa!17319> (cherry picked from commit 90c5eea2)
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update_renames() fills in the wrong temp id. Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> Fixes: 302cb5c9 ("aco/ra: remove some redundant code") Part-of: <mesa/mesa!17295> (cherry picked from commit 84f04fd0)
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Dylan Baker authored
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- Jun 30, 2022
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interface blocks can have row_major set cc: mesa-stable affects (zink): dEQP-GLES2.functional.shaders* Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com> Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com> Part-of: <mesa/mesa!17238> (cherry picked from commit 0e7863c3)
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Dylan Baker authored
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- Jun 29, 2022
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Dylan Baker authored
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The feature we wanted to enable in 710393b3 was descriptorBindingUniformBufferUpdateAfterBind. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes: 710393b3 ("anv: enable UBO indexing") Reviewed-by: Francisco Jerez <currojerez@riseup.net> Part-of: <mesa/mesa!17200> (cherry picked from commit 3e247cd0)
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Dylan Baker authored
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Dylan Baker authored
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Dylan Baker authored
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Dylan Baker authored
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- Jun 28, 2022
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Extend the packed_instr struct to support texops above nir_texop_fragment_fetch_amd. Fixes: 603e6ba9 ("nir: add two new texture ops for multisample fragment color/mask fetches") Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com> Part-of: <mesa/mesa!17186> (cherry picked from commit 370ca074)
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The postponed spill is predicated using the condition from the last write, but this is only correct if the register was only written once in the TMU sequence, or if it is always written with the same predication. While we could try to track whether this is the case or not, it would make the postponed spill path even more complex than it already is, so let's just avoid predicating these. We are already discouraging TMU spilling of registers in the middle of TMU sequences, so this should not be a very common case. Cc: mesa-stable Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com> Part-of: <mesa/mesa!17201> (cherry picked from commit cfccd93e)
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If we are spilling a register that is used in the middle of a TMU sequence, we postpone the spill until the TMU sequence finishes, at which point we inject the spill and rewrite the original instruction to write to the new temp. However, this doesn't work if the register is written multiple times during the TMU sequence. In that scenario, we need to ensure that all writes are rewritten to use the new temp, not just the last one. Cc: mesa-stable Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com> Part-of: <mesa/mesa!17201> (cherry picked from commit 98420408)
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Cc: mesa-stable Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com> Part-of: <mesa/mesa!17201> (cherry picked from commit 0bc65b1d)
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