Signed-off-by: Dave Airlie <airlied@redhat.com>

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

nvc0 sets the NVC0_IB_ENTRY_1_NO_PREFETCH bit on some pushbuffers

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

ci: use `base-devel` tag of archlinux image instead of `base` and then installing `base-devel` after

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Simon Ser <contact@emersion.fr>

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Simon Ser <contact@emersion.fr>

This reverts commit b3628506.

This breaks when the kernel driver does not support modifiers and the
application properly zeroes the modifiers.

Acked-by: Simon Ser <contact@emersion.fr>

In syncobj test, 3 threads will be created. Sometimes
the first gfx IB and the third sdma IB will use same
physical page. There will be risk that sdma engine will
read gfx IB in the same physical page. So better to flush
the cache before commit the sdma IB.

Signed-off-by: Jinzhou Su <Jinzhou.Su@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>

Huang Rui authored 3 years ago and Pierre-Eric Pelloux-Prayer committed 3 years ago

Using tmz ids that reported from kernel to decide whether enable
security tests.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

James Zhu authored 3 years ago and Alex Deucher committed 3 years ago

VCN is supported after AI family Arcturus.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>

Retire the asic_id check for AI family.

Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>

buffer_load/store_format_xyzw require 64bit vgpr_a[2].
The original parameter is one u32. Modify the shader binary to
fit the 64bit parameter.

Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Tested-by: Gang Long <Gang.Long@amd.com>

Signed-off-by: Leo Liu <leo.liu@amd.com>

via the newly added uapi/amdgpu_drm interface

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

From drm-next:

commit 2cbcb78c9ee5520c8d836c7ff57d1b60ebe8e9b7
Merge: 06debd6e1b28 8c44390d8872
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date:   Fri Mar 26 15:52:01 2021 +0100

    Merge tag 'amd-drm-next-5.13-2021-03-23' of https://gitlab.freedesktop.org/agd5f/linux into drm-next

    amd-drm-next-5.13-2021-03-23:

    amdgpu:
    ...

    UAPI:
    - amdgpu: Add a new INFO ioctl interface to query video capabilities
      rather than hardcoding them in userspace.  This allows us to provide
      fine grained asic capabilities (e.g., if a particular part is
      bandwidth limited, we can limit the capabilities).  Proposed userspace:
      https://gitlab.freedesktop.org/leoliu/drm/-/commits/info_video_caps
      https://gitlab.freedesktop.org/leoliu/mesa/-/commits/info_video_caps


    ...

    Danvet: A bunch of conflicts all over, but it seems to compile ... I
    did put the call to dc_allow_idle_optimizations() on a single line
    since it looked a bit too jarring to be left alone.

Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
    From: Alex Deucher <alexander.deucher@amd.com>
    Link: https://patchwork.freedesktop.org/patch/msgid/20210324040147.1990338-1-alexander.deucher@amd.com



Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

The kernel will always return EINVAL if modifiers are supplied but
the flag DRM_MODE_FB_MODIFIERS isn't set. That's a pretty nice
footgun.

Be a little more helpful and set the flag if the user has supplied
a modifier array.

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

On Raven2/Picasso, the default VRAM size is 2048M,
and the default GTT size is 3072M. If max_allocation
of VRAM exceeds half of GTT size, GTT memory can't
hold evicted bo from VRAM and bo in itself at the
same time. Then amdgpu_cs_list_validate will failed
with "Not enough memory for command submission" error.

NOTE:
The installed DRAM should be larger than 8GB,
if the VRAM size is 2048M.

Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>

The unit of size_metadata is one byte not four bytes.
Enable Metadata test.

Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>

We already have drm_property_type_is, but it's needlessly complicated
and doesn't cover all use-cases (requires the caller to provide a
type).

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

In syncobj test, wait thread and signal thread create
simultaneously. The ptr for GFX IB and SDMA IP should be
operated separately. With static, there will be risk that
GFX NOP is in SDMA IB or SDMA NOP is in GFX IB, then GFX or
SDMA hang caused.

Signed-off-by: Jinzhou Su <Jinzhou.Su@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>

The general direction at this time is to phase out pread/write ioctls and
not support them in future products. The ioctls have already been disabled
in i915 for future products. This means libdrm must handle the absence of
these ioctls. This patch does this by modifying drm_intel_gem_bo_subdata()
and drm_intel_gem_bo_get_subdata() to do the read/write using the
pread/pwrite ioctls first but when these ioctls are unavailable fall back
to doing the read/write using a combination of mmap and memcpy.

A similar solution was added to igt-gpu-tools in commit
ad5eb02eb3 ("lib/ioctl_wrappers: Keep IGT working without pread/pwrite
ioctls").

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>

This allows users to select the library type (static or shared)
using the Meson -Ddefault_library built-in option.

Issue: #45



Reviewed-by: Simon Ser <contact@emersion.fr>
Signed-off-by: Fang Tan <tanfang@uniontech.com>

If info.count is large, drmMalloc() / alloca() may fail, and the
resulting null pointer is not null checked before dereference.

Issue: mesa/drm#62



Reviewed-by: Simon Ser <contact@emersion.fr>
Signed-off-by: Alistair Delva <adelva@google.com>

Add the PCI ID import for JSL.

V1 - Indentation
Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

Do as the documentation says - when devices non NULL, cap the reported
devices to max_devices. Otherwise we risk out-of-bound access
for users of the API.

v2:
 - Fix this w/o breaking the API

v3:
 - Drop local variables, flip inverted conditional (Simon)

Issue: mesa/drm#56


Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Simon Ser <contact@emersion.fr>

This reverts commit 8cb12a25.

The commit fixed the OOB, yet it broke drmDevices2(0, NULL, 0) - aka we
did not return the total devices list.

Reviewed-by: Simon Ser <contact@emersion.fr>

Simon Ser authored 3 years ago and Emil Velikov committed 3 years ago

Users need to be careful when using drmPrimeHandleToFD or
drmPrimeFDToHandle directly. Mention GBM as a solution.

See [1] for an example mistake.

[1]: drm/nouveau#43 (comment 772661)



Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>

If a device has a primary node, it doesn't necessarily mean it's
suitable for KMS usage. For instance, render-only drivers also
expose primary nodes.

The check is extracted from Weston [1].

The motivation for this new function is two-fold:

- Avoid an unnecessary GETRESOURCES call. To check whether a
  primary node is suitable for KMS, we don't actually need to
  retrieve the object IDs we just need to check the counts.
- Avoid confusion in user-space and make sure user-space implements
  the check properly. For instance, wlroots doesn't [2]: it uses
  drmGetVersion which succeeds with render-only drivers.

[1]: https://gitlab.freedesktop.org/wayland/weston/-/blob/master/libweston/backend-drm/drm.c#L2689
[2]: https://github.com/swaywm/wlroots/blob/a290d7a78dc36275e24e54f84570f37a66dc67a4/backend/session/session.c#L268



Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Pekka Paalanen <pekka.paalanen@collabora.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

amdgpu_drm: sync up with the latest amdgpu_drm.h based on drm-next (https://cgit.freedesktop.org/drm/drm)

What are these headers?
Adding currently missing stuff from https://cgit.freedesktop.org/drm/drm/tree/include/uapi/drm/amdgpu_drm.h based on
the latest commit there:

commit f730f39eb981af249d57336b47cfe3925632a7fd (HEAD -> drm-next, tag: drm-next-2021-02-19, origin/drm-next, origin/HEAD)
Merge: 4f8ad4045b38 81ce8f04aa96
Author: Dave Airlie <airlied@redhat.com>
Date:   Fri Feb 19 13:54:29 2021 +1000

    Merge tag 'drm-intel-next-fixes-2021-02-18' of git://anongit.freedesktop.org/drm/drm-intel into drm-next

Which headers go where?
From https://cgit.freedesktop.org/drm/drm/tree/include/uapi/drm/amdgpu_drm.h to
https://cgit.freedesktop.org/mesa/drm/tree/include/drm/amdgpu_drm.h

When and which headers to update?
If the kernel uapi drm header changes, the header here should be sync-ed.

When and how to update these files
The steps for generating this patch:

 - Switch to freedesktop drm-next kernel branch (https://cgit.freedesktop.org/drm/drm);
 - Install the headers via `make headers_install';
 - Copy from kernel "include/uapi/drm/amdgpu_drm.h" to libdrm "include/drm/amdgpu_drm.h";
 - generate the patch;

The commits from drm-next (https://cgit.freedesktop.org/drm/drm

) are:

Mauro Carvalho Chehab (1)
c45dd3bda1c809eb120452597097e14a96b58c1f drm/amdgpu: fix some kernel-doc markups

Huang Rui(3)
6fbcb00c7984fa7d49af2c361453c0397cdea400 drm/amdgpu: add TOC firmware definition
1e483203965bdab466af0739c1edf7da07da241d drm/amdgpu: add uapi to define van gogh memory type
f7b2cdb23abf62bc3d33c2e0b0009a09412ff475 drm/amdgpu: add uapi to define van gogh series

Pierre-Eric Pelloux-Prayer(1)
16c642ec3fe9a144fbe1e97dc56f13a6308f1381 drm/amdgpu: new ids flag for tmz (v2)

Yong Zhao(1)
130c88931f6cbdb4513d307b4a13fcfff08a8041 drm/amdgpu: Improve the MTYPE comments

Signed-off-by: Leo Liu <leo.liu@amd.com>

Tejas Upadhyay authored 3 years ago and Lionel Landwerlin committed 3 years ago

This enables drm_intel_bufmgr on ADLS

Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

Align with kernel commits:

0883d63b19bb ("drm/i915/adl_s: Add ADL-S platform info and PCI ids")
04057a1afc75 ("drm/i915: Sort EHL/JSL PCI IDs")
0e8e272f1368 ("drm/i915/ehl: Remove invalid PCI ID")
605f9c290c1a ("drm/i915: Sort ICL PCI IDs")
514dc424ce4f ("drm/i915: Sort CNL PCI IDs")
32d4ec9a1681 ("drm/i915: Sort CFL PCI IDs")
df3478af1d73 ("drm/i915: Sort CML PCI IDs")
cd988984cbea ("drm/i915: Sort KBL PCI IDs")
b04d36f73771 ("drm/i915: Sort SKL PCI IDs")
9c0b2d30441b ("drm/i915: Sort HSW PCI IDs")
79033a0a7898 ("drm/i915: Ocd the HSW PCI ID hex numbers")
cfb3db8fdae2 ("drm/i915: Try to fix the SKL GT3/4 vs. GT3e/4e comments")
03e399020cd2 ("drm/i915: Add SKL GT1.5 PCI IDs")
812f044df08c ("drm/i915: Reclassify SKL 0x1923 and 0x1927 as ULT")
194909a32aed ("drm/i915: Reclassify SKL 0x192a as GT3")
82e84284ab7d ("drm/i915: Update Haswell PCI IDs")
24ea098b7c0d ("drm/i915/jsl: Split EHL/JSL platform info and PCI ids")
b50b7991b739 ("drm/i915/dg1: add more PCI ids")
d452bd091e16 ("drm/i915: break TGL pci-ids in GT 1 & 2")
f2bde2546b81 ("drm/i915: Remove dubious Valleyview PCI IDs")
0883d63b19bb ("drm/i915/adl_s: Add ADL-S platform info and PCI ids")
04057a1afc75 ("drm/i915: Sort EHL/JSL PCI IDs")
0e8e272f1368 ("drm/i915/ehl: Remove invalid PCI ID")
605f9c290c1a ("drm/i915: Sort ICL PCI IDs")
514dc424ce4f ("drm/i915: Sort CNL PCI IDs")
32d4ec9a1681 ("drm/i915: Sort CFL PCI IDs")
df3478af1d73 ("drm/i915: Sort CML PCI IDs")
cd988984cbea ("drm/i915: Sort KBL PCI IDs")
b04d36f73771 ("drm/i915: Sort SKL PCI IDs")
9c0b2d30441b ("drm/i915: Sort HSW PCI IDs")
79033a0a7898 ("drm/i915: Ocd the HSW PCI ID hex numbers")
cfb3db8fdae2 ("drm/i915: Try to fix the SKL GT3/4 vs. GT3e/4e comments")
03e399020cd2 ("drm/i915: Add SKL GT1.5 PCI IDs")
812f044df08c ("drm/i915: Reclassify SKL 0x1923 and 0x1927 as ULT")
194909a32aed ("drm/i915: Reclassify SKL 0x192a as GT3")
82e84284ab7d ("drm/i915: Update Haswell PCI IDs")
24ea098b7c0d ("drm/i915/jsl: Split EHL/JSL platform info and PCI ids")
b50b7991b739 ("drm/i915/dg1: add more PCI ids")
d452bd091e16 ("drm/i915: break TGL pci-ids in GT 1 & 2")

Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
Reviewed-by: Landwerlin, Lionel G <lionel.g.landwerlin@intel.com>

From 20.45 release.

Acked-by: Simon Ser <contact@emersion.fr>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Victor Hugo Vianna Silva authored 3 years ago and Simon Ser committed 3 years ago

- Remove one unused variable.
- Convert two int-s into 'unsigned int'.
Motivated by a failed build of Chromium.

Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Victor Hugo Vianna Silva <victor.vianna10@gmail.com>

Do as the documentation says - cap the number of reported devices to the
requested amount - aka max_devices. Otherwise we risk out-of-bound access
for users of the API.

Issue: mesa/drm#56


Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Simon Ser <contact@emersion.fr>

Sonny Jiang authored 3 years ago and Leo Liu committed 3 years ago

Remove useless codes.

Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

James Zhu authored 4 years ago and Leo Liu committed 3 years ago

add dimgrey_cavefish chip id in vcn test

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>

Tao Zhou authored 4 years ago and Leo Liu committed 3 years ago

add navy_flounder chip id in vcn test

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>