1. 03 Apr, 2021 2 commits
  2. 01 Apr, 2021 2 commits
  3. 31 Mar, 2021 1 commit
  4. 24 Mar, 2021 1 commit
  5. 22 Mar, 2021 1 commit
    • Ashutosh Dixit's avatar
      intel: Keep libdrm working without pread/pwrite ioctls · cd368197
      Ashutosh Dixit authored
      
      
      The general direction at this time is to phase out pread/write ioctls and
      not support them in future products. The ioctls have already been disabled
      in i915 for future products. This means libdrm must handle the absence of
      these ioctls. This patch does this by modifying drm_intel_gem_bo_subdata()
      and drm_intel_gem_bo_get_subdata() to do the read/write using the
      pread/pwrite ioctls first but when these ioctls are unavailable fall back
      to doing the read/write using a combination of mmap and memcpy.
      
      A similar solution was added to igt-gpu-tools in commit
      ad5eb02eb3 ("lib/ioctl_wrappers: Keep IGT working without pread/pwrite
      ioctls").
      Reviewed-by: Jason Ekstrand's avatarJason Ekstrand <jason@jlekstrand.net>
      Signed-off-by: Ashutosh Dixit's avatarAshutosh Dixit <ashutosh.dixit@intel.com>
      cd368197
  6. 09 Mar, 2021 1 commit
  7. 02 Mar, 2021 2 commits
  8. 26 Feb, 2021 4 commits
  9. 21 Feb, 2021 1 commit
  10. 18 Feb, 2021 2 commits
    • Tejas Upadhyay's avatar
      intel: add INTEL_ADLS_IDS to the pciids list · 3b6cfb20
      Tejas Upadhyay authored and Lionel Landwerlin's avatar Lionel Landwerlin committed
      
      
      This enables drm_intel_bufmgr on ADLS
      Signed-off-by: Tejas Upadhyay's avatarTejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
      Reviewed-by: Lionel Landwerlin's avatarLionel Landwerlin <lionel.g.landwerlin@intel.com>
      3b6cfb20
    • Tejas Upadhyay's avatar
      intel: sync i915_pciids.h with kernel · 9086ff9d
      Tejas Upadhyay authored
      
      
      Align with kernel commits:
      
      0883d63b19bb ("drm/i915/adl_s: Add ADL-S platform info and PCI ids")
      04057a1afc75 ("drm/i915: Sort EHL/JSL PCI IDs")
      0e8e272f1368 ("drm/i915/ehl: Remove invalid PCI ID")
      605f9c290c1a ("drm/i915: Sort ICL PCI IDs")
      514dc424ce4f ("drm/i915: Sort CNL PCI IDs")
      32d4ec9a1681 ("drm/i915: Sort CFL PCI IDs")
      df3478af1d73 ("drm/i915: Sort CML PCI IDs")
      cd988984cbea ("drm/i915: Sort KBL PCI IDs")
      b04d36f73771 ("drm/i915: Sort SKL PCI IDs")
      9c0b2d30441b ("drm/i915: Sort HSW PCI IDs")
      79033a0a7898 ("drm/i915: Ocd the HSW PCI ID hex numbers")
      cfb3db8fdae2 ("drm/i915: Try to fix the SKL GT3/4 vs. GT3e/4e comments")
      03e399020cd2 ("drm/i915: Add SKL GT1.5 PCI IDs")
      812f044df08c ("drm/i915: Reclassify SKL 0x1923 and 0x1927 as ULT")
      194909a32aed ("drm/i915: Reclassify SKL 0x192a as GT3")
      82e84284ab7d ("drm/i915: Update Haswell PCI IDs")
      24ea098b7c0d ("drm/i915/jsl: Split EHL/JSL platform info and PCI ids")
      b50b7991b739 ("drm/i915/dg1: add more PCI ids")
      d452bd091e16 ("drm/i915: break TGL pci-ids in GT 1 & 2")
      f2bde2546b81 ("drm/i915: Remove dubious Valleyview PCI IDs")
      0883d63b19bb ("drm/i915/adl_s: Add ADL-S platform info and PCI ids")
      04057a1afc75 ("drm/i915: Sort EHL/JSL PCI IDs")
      0e8e272f1368 ("drm/i915/ehl: Remove invalid PCI ID")
      605f9c290c1a ("drm/i915: Sort ICL PCI IDs")
      514dc424ce4f ("drm/i915: Sort CNL PCI IDs")
      32d4ec9a1681 ("drm/i915: Sort CFL PCI IDs")
      df3478af1d73 ("drm/i915: Sort CML PCI IDs")
      cd988984cbea ("drm/i915: Sort KBL PCI IDs")
      b04d36f73771 ("drm/i915: Sort SKL PCI IDs")
      9c0b2d30441b ("drm/i915: Sort HSW PCI IDs")
      79033a0a7898 ("drm/i915: Ocd the HSW PCI ID hex numbers")
      cfb3db8fdae2 ("drm/i915: Try to fix the SKL GT3/4 vs. GT3e/4e comments")
      03e399020cd2 ("drm/i915: Add SKL GT1.5 PCI IDs")
      812f044df08c ("drm/i915: Reclassify SKL 0x1923 and 0x1927 as ULT")
      194909a32aed ("drm/i915: Reclassify SKL 0x192a as GT3")
      82e84284ab7d ("drm/i915: Update Haswell PCI IDs")
      24ea098b7c0d ("drm/i915/jsl: Split EHL/JSL platform info and PCI ids")
      b50b7991b739 ("drm/i915/dg1: add more PCI ids")
      d452bd091e16 ("drm/i915: break TGL pci-ids in GT 1 & 2")
      Signed-off-by: Tejas Upadhyay's avatarTejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
      Reviewed-by: Lionel Landwerlin's avatarLandwerlin, Lionel G <lionel.g.landwerlin@intel.com>
      9086ff9d
  11. 15 Feb, 2021 1 commit
  12. 10 Feb, 2021 2 commits
  13. 23 Jan, 2021 3 commits
  14. 22 Jan, 2021 1 commit
  15. 21 Jan, 2021 1 commit
  16. 11 Jan, 2021 5 commits
  17. 12 Dec, 2020 1 commit
  18. 11 Dec, 2020 2 commits
  19. 10 Dec, 2020 3 commits
  20. 09 Dec, 2020 3 commits
  21. 06 Nov, 2020 1 commit