- Sep 09, 2024
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Without EXTRA_CARGO_ARGS='--target armv7-unknown-linux-gnueabihf', deqp-runner binary was built for aarch64 architecture for arm32 builds and causing below failures on arm32 target, /usr/bin/deqp-runner: cannot execute binary file: Exec format error So pass EXTRA_CARGO_ARGS to cargo to fix this. Fixes: 83d9cfa5 ("ci/deqp-runner: build from git checkout even on linux") Signed-off-by:
Vignesh Raman <vignesh.raman@collabora.com> Part-of: <mesa/mesa!31071>
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Mary Guillemard authored
Signed-off-by:
Mary Guillemard <mary.guillemard@collabora.com> Part-of: <mesa/mesa!30553>
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Mary Guillemard authored
This implement PIPE_CAP_QUERY_TIMESTAMP, PIPE_CAP_QUERY_TIME_ELAPSED and PIPE_CAP_TIMER_RESOLUTION by using the new uAPI in place. Effectively, this expose ARB_timer_query, EXT_disjoint_timer_query and OpenCL profiling on rusticl. Co-authored-by:
Antonino Maniscalco <antonino.maniscalco@collabora.com> Signed-off-by:
Mary Guillemard <mary.guillemard@collabora.com> Reviewed-by:
Louis-Francis Ratté-Boulianne <lfrb@collabora.com> Part-of: <!30553>
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Mary Guillemard authored
Also ensure to check if resource allocation failed. Signed-off-by:
Mary Guillemard <mary.guillemard@collabora.com> Reviewed-by:
Louis-Francis Ratté-Boulianne <lfrb@collabora.com> Part-of: <!30553>
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Mary Guillemard authored
This adds support for timestamp in kmod based on new uAPI changes. Signed-off-by:
Mary Guillemard <mary.guillemard@collabora.com> Reviewed-by:
Louis-Francis Ratté-Boulianne <lfrb@collabora.com> Part-of: <!30553>
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Mary Guillemard authored
Update to sync with uAPI changes. Signed-off-by:
Mary Guillemard <mary.guillemard@collabora.com> Reviewed-by:
Louis-Francis Ratté-Boulianne <lfrb@collabora.com> Part-of: <mesa/mesa!30553>
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Mary Guillemard authored
Update to sync with uAPI changes. Signed-off-by:
Mary Guillemard <mary.guillemard@collabora.com> Reviewed-by:
Louis-Francis Ratté-Boulianne <lfrb@collabora.com> Part-of: <mesa/mesa!30553>
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- Sep 08, 2024
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David Rosca authored
The begin op was sent as one task and encode op as another one. This doesn't work on VCN2 and older, so just send both ops in same task. Reviewed-by:
Dave Airlie <airlied@redhat.com> Part-of: <mesa/mesa!31078>
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David Rosca authored
This should only be used on video session destroy, but at that point we don't have command buffer. RENCODE_IB_OP_CLOSE_SESSION is optional, so it's okay not using it at all. Reviewed-by:
Dave Airlie <airlied@redhat.com> Part-of: <mesa/mesa!31078>
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- Sep 07, 2024
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Add missing @eot to the example. Reword INTEL_DEBUG=color description. Part-of: <mesa/mesa!31076>
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Part-of: <mesa/mesa!31070>
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this was broken by various things Part-of: <mesa/mesa!31070>
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Enabling this gives slight increase in quality. Reviewed-by:
Ruijing Dong <ruijing.dong@amd.com> Part-of: <!31020>
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It only makes it more likely to forget updating all functions when implementing these features and cause issues. Also fixes H264 constrained_intra_pred on VCN5. Reviewed-by:
Ruijing Dong <ruijing.dong@amd.com> Part-of: <!31020>
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Also use constrained_intra_pred_flag from pic params. Reviewed-by:
Ruijing Dong <ruijing.dong@amd.com> Part-of: <mesa/mesa!31020>
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"GL2" is also OK. "TC-compatible" is also OK. Acked-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <mesa/mesa!30869>
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Acked-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <mesa/mesa!30869>
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not a serious issue because we only use it for PRIME without SDMA IIRC Acked-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <mesa/mesa!30869>
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thanks Mike Signed-off-by:Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <!30934>
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Same code generated on AGX but simplified NIR. Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by:
Georg Lehmann <dadschoorse@gmail.com> Part-of: <!30934>
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this existed due to the min/max, per the comment. now that we don't do min/max, the whole routine is NaN correct so the fixup is pointless. Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Suggested-by:
Ian Romanick <ian.d.romanick@intel.com> Reviewed-by:
Georg Lehmann <dadschoorse@gmail.com> Part-of: <mesa/mesa!30934>
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everybody has abs on fmul, not everyone has abs on bcsel. should help agx and bifrost. Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by:
Ian Romanick <ian.d.romanick@intel.com> Part-of: <mesa/mesa!30934>
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Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by:
Ian Romanick <ian.d.romanick@intel.com> Part-of: <mesa/mesa!30934>
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we're going to fix up the sign immediately anyway. Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by:
Ian Romanick <ian.d.romanick@intel.com> Part-of: <mesa/mesa!30934>
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the original version sure is creative. Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by:
Ian Romanick <ian.d.romanick@intel.com> Part-of: <mesa/mesa!30934>
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this does two things: * ignores sign of negative numbers which let us play fast and loose later in th series * avoids an expensive fsign instruction in favour of a cheap bitwise op Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by:
Ian Romanick <ian.d.romanick@intel.com> Part-of: <mesa/mesa!30934>
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Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by:
Ian Romanick <ian.d.romanick@intel.com> Part-of: <!30934>
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worse in terms of NIR instruction count but lets the fabs fold easier. (on agx, which has fabs on comparisons and fmul but not on bcsel. should be no worse if ISA has fabs on all 3.) Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by:
Ian Romanick <ian.d.romanick@intel.com> Part-of: <mesa/mesa!30934>
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just implement what the comment says, don't be clever. the clever thing is worse on all architectures i'm familiar with, because the fdiv will turn into fmul+frcp. Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by:
Ian Romanick <ian.d.romanick@intel.com> Part-of: <mesa/mesa!30934>
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the code did not match the comment, blew a sign. Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by:
Ian Romanick <ian.d.romanick@intel.com> Part-of: <mesa/mesa!30934>
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Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by:
Ian Romanick <ian.d.romanick@intel.com> Part-of: <mesa/mesa!30934>
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Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by:
Georg Lehmann <dadschoorse@gmail.com> Part-of: <mesa/mesa!30934>
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for vgpu9 but not 10 Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by:
Georg Lehmann <dadschoorse@gmail.com> Part-of: <mesa/mesa!30934>
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Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by:
Georg Lehmann <dadschoorse@gmail.com> Part-of: <mesa/mesa!30934>
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Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by:
Georg Lehmann <dadschoorse@gmail.com> Part-of: <mesa/mesa!30934>
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Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by:
Georg Lehmann <dadschoorse@gmail.com> Part-of: <mesa/mesa!30934>
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- Sep 06, 2024
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PPS header should use pps_loop_filter_across_slices_enabled_flag instead of slice_loop_filter_across_slices_enabled_flag according to HEVC SPEC. Slice header should also use pps_loop_filter_across_slices_enabled_flag as one of the condition to determine if slice flag needs to be present. V2: Apply pps_loop_filter_across_slices_enabled_flag to loop_filter as well So modify loop_filter_across_slices_enabled value to be pps one instead Signed-off-by:
Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by:
David Rosca <david.rosca@amd.com> Reviewed-by:
Ruijing Dong <ruijing.dong@amd.com> Part-of: <!31064>
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Fixes: f1fdffa1 (nvk: Support image creation with modifiers) Part-of: <mesa/mesa!31045>
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Fix definitions of PIPE_BIND_VIDEO_DECODE/ENCODE_DPB as they conflict with PIPE_BIND_SCANOUT and PIPE_BIND_SHARED Fixes: f8145fe6 ("pipe: Add PIPE_BIND_VIDEO_DECODE_DPB/PIPE_BIND_VIDEO_ENCODE_DPB") Reviewed-by:
Jesse Natalie <jenatali@microsoft.com> Reviewed-by:
Karol Herbst <kherbst@redhat.com> Part-of: <mesa/mesa!31067>
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There are two bugs: - VK_KHR_maintenance5 added VkBufferUsageFlags2CreateInfoKHR, so checking for pCreateInfo->usage is incomplete - this was also missing the usage flag for descriptor buffer with samplers This fixes recent VKCTS coverage in dEQP-VK.binding_model.descriptor_buffer.*. Fixes: 059391b6 ("radv: use 32bit va range for sparse descriptor buffers") Signed-off-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <mesa/mesa!31054>
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