- Mar 21, 2025
-
-
Asad Kamal authored
Update feature list for smu_v13_0_6 to show vcn & smu deep sleep feature enable status Signed-off-by:
Asad Kamal <asad.kamal@amd.com> Reviewed-by:
Yang Wang <kevinyang.wang@amd.com> Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
-
SRINIVASAN SHANMUGAM authored
The 'flags' parameter, which specifies memory allocation behavior while creating a sync entry, Fixes the below with gcc W=1: drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c:162: warning: Function parameter or struct member 'flags' not described in 'amdgpu_sync_fence' Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
-
Alex Deucher authored
On chips without native IP discovery support, use the fw binary if available, otherwise we can continue without it. Signed-off-by:
Flora Cui <flora.cui@amd.com> Signed-off-by:
-
fcui authored
vega10/vega12/vega20/raven/raven2/picasso/arcturus/aldebaran Signed-off-by:
-
fcui authored
Signed-off-by:
-
Asad Kamal authored
Few of the metrics data for smu_v13_0_12 has not been reported in Q10 format, remove UQ10 to UINT conversion for those Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
-
Asad Kamal authored
Few of the metrics data for smu_v13_0_6 has not been reported in Q10 format, remove UQ10 to UINT conversion for those v2: Move smu_v13_0_12 changes to separate patch(Kevin) Signed-off-by:
-
Jie1zhang authored
This commit updates the VM flush implementation for the SDMA engine. - Added a new function `sdma_v4_4_2_get_invalidate_req` to construct the VM_INVALIDATE_ENG0_REQ register value for the specified VMID and flush type. This function ensures that all relevant page table cache levels (L1 PTEs, L2 PTEs, and L2 PDEs) are invalidated. - Modified the `sdma_v4_4_2_ring_emit_vm_flush` function to use the new `sdma_v4_4_2_get_invalidate_req` function. The updated function emits the necessary register writes and waits to perform a VM flush for the specified VMID. It updates the PTB address registers and issues a VM invalidation request using the specified VM invalidation engine. - Included the necessary header file `gc/gc_9_0_sh_mask.h` to provide access to the required register definitions. v2: vm flush by the vm inalidation packet (Lijo) v3: code stle and define thh macro for the vm invalidation packet (Christian) v4: Format definition sdma vm invalidate packet (Lijo) Suggested-by:
Jesse Zhang <jesse.zhang@amd.com> Reviewed-by:
-
Jie1zhang authored
- Modify the VM invalidation engine allocation logic to handle SDMA page rings. SDMA page rings now share the VM invalidation engine with SDMA gfx rings instead of allocating a separate engine. This change ensures efficient resource management and avoids the issue of insufficient VM invalidation engines. - Add synchronization for GPU TLB flush operations in gmc_v9_0.c. Use spin_lock and spin_unlock to ensure thread safety and prevent race conditions during TLB flush operations. This improves the stability and reliability of the driver, especially in multi-threaded environments. v2: replace the sdma ring check with a function `amdgpu_sdma_is_page_queue` to check if a ring is an SDMA page queue.(Lijo) v3: Add GC version check, only enabled on GC9.4.3/9.4.4/9.5.0 v4: Fix code style and add more detailed description (Christian) v5: Remove dependency on vm_inv_eng loop order, explicitly lookup shared inv_eng(Christian/Lijo) v6: Added search shared ring function amdgpu_sdma_get_shared_ring (Lijo) Suggested-by:
-
Jie1zhang authored
Increase the maximum number of rings supported by the AMDGPU driver from 133 to 149. This change is necessary to enable support for the SDMA page ring. Signed-off-by:
-
Xiang Liu authored
In the case of injecting uncorrected error with background workload, the deferred error among uncorrected errors need to be specified by checking the deferred and poison bits of status register. v2: refine checking for deferred error v2: log possiable DEs among CEs v2: generate CPER records for DEs among UEs Signed-off-by:
Xiang Liu <xiang.liu@amd.com> Reviewed-by:
-
SRINIVASAN SHANMUGAM authored
Enable the cleaner shader for GFX11.5.0/11.5.1 GPUs to provide data isolation between GPU workloads. The cleaner shader is responsible for clearing the Local Data Store (LDS), Vector General Purpose Registers (VGPRs), and Scalar General Purpose Registers (SGPRs), which helps prevent data leakage and ensures accurate computation results. This update extends cleaner shader support to GFX11.5.0/11.5.1 GPUs, previously available for GFX11.0.3. It enhances security by clearing GPU memory between processes and maintains a consistent GPU state across KGD and KFD workloads. Cc: Mario Sopena-Novales <mario.novales@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
-
Alex Deucher authored
Follow the same logic as the other IP types. Reviewed-by:
Prike Liang <Prike.Liang@amd.com> Acked-by:
-
Alex Deucher authored
Enable pipes on both MECs for MES. Fixes: 745f46b6 ("drm/amdgpu: enable mes v12 self test") Acked-by:
-
Alex Deucher authored
Leftover from MES bring up. There is no production MES support for MES 10.x. The rest of the MES 10.x code has already been removed so drop this. Acked-by:
-
Alex Deucher authored
Break when we get to the end of the supported pipes rather than continuing the loop. Reviewed-by:
Shaoyun.liu <Shaoyun.liu@amd.com> Signed-off-by:
-
Alex Deucher authored
The gfx and page queues are per instance, so track them per instance. v2: drop extra parameter (Lijo) Fixes: fdbfaaaa ("drm/amdgpu: Improve SDMA reset logic with guilty queue tracking") Reviewed-by:
-
Alex Deucher authored
Move the kfd suspend/resume code into the caller. That is where the KFD is likely to detect a reset so on the KFD side there is no need to call them. Also add a mutex to lock the actual reset sequence. v2: make the locking per instance Fixes: bac38ca8 ("drm/amdkfd: implement per queue sdma reset for gfx 9.4+") Reviewed-by:
-
Christian König authored
I can't count how often I had to remove this nonsense. Probably doesn't need an explanation any more. Signed-off-by:
-
Christian König authored
Note when the cleaner shader is executed. Signed-off-by:
-
Christian König authored
Note when we switch from one isolation owner to another. Signed-off-by:
-
Christian König authored
That was quite troublesome for gang submit. Completely drop this approach and enforce the isolation separately. Signed-off-by:
-
Christian König authored
Instead of emitting the cleaner shader for every job which has the enforce_isolation flag set only emit it for the first submission from every client. v2: add missing NULL check v3: fix another NULL pointer deref Signed-off-by:
-
Christian König authored
Limiting the number of available VMIDs to enforce isolation causes some issues with gang submit and applying certain HW workarounds which require multiple VMIDs to work correctly. So instead start to track all submissions to the relevant engines in a per partition data structure and use the dma_fences of the submissions to enforce isolation similar to what a VMID limit does. v2: use ~0l for jobs without isolation to distinct it from kernel submissions which uses NULL for the owner. Add some warning when we are OOM. Signed-off-by: -
Christian König authored
This allows using amdgpu_sync even without peeking into the fences for a long time. Signed-off-by:
-
Christian König authored
In the critical submission path memory allocations can't wait for reclaim since that can potentially wait for submissions to finish. Finally clean that up and mark most memory allocations in the critical path with GFP_NOWAIT. The only exception left is the dma_fence_array() used when no VMID is available, but that will be cleaned up later on. Signed-off-by:
-
Kenneth Feng authored
This reverts commit 55ff973f. Reason for revert: this causes some tests fail with call trace. Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Acked-by:
-
Ahmad Rehman authored
For SRIOV, skip the SDMA queue reset and return error. The engine/queue reset failure will trigger FLR in the sequence. v2: do not add queue reset support mask for sriov Signed-off-by:
Ahmad Rehman <Ahmad.Rehman@amd.com> Reviewed-by:
-
Ahmad Rehman authored
Add case for 13.0.12. Signed-off-by:
Ahmad Rehman <ahrehman@amd.com> Reviewed-by:
<Vignesh.Chander@amd.com> Signed-off-by:
-
Ellen Pan authored
This enables ras to be resumed after gpu recovery on mi350 sriov. Signed-off-by:
Ellen Pan <yunru.pan@amd.com> Reviewed-by:
-
jokim-amd authored
Clause instructions with precise memory enabled currently hang the shader so set capabilities flag to disabled since it's unsafe to use for debugging. Signed-off-by:
Jonathan Kim <jonathan.kim@amd.com> Tested-by:
Lancelot Six <lancelot.six@amd.com> Reviewed-by:
Harish Kasiviswanathan <harish.kasiviswanathan@amd.com> Signed-off-by:
-
- Mar 19, 2025
-
-
Victor Skvortsov authored
VFs cannot read the NAK_COUNTER register. This information is only available through PMFW metrics. Signed-off-by:
Victor Skvortsov <victor.skvortsov@amd.com> Reviewed-by:
-
Candice Li authored
Add active_umc_mask to ras init_flags. Signed-off-by:
Candice Li <candice.li@amd.com> Reviewed-by:
-
lijo lazar authored
Add description for debug_mask bit options. Signed-off-by:
-
lijo lazar authored
In certain cases, it's desirable to avoid PMFW log transactions to system memory. Add a mask bit to decide whether to allocate smu pool in device memory or system memory. Signed-off-by:
-
Alex Deucher authored
No need to make the workload profile setup dependent on the results of cancelling the delayed work thread. We have all of the necessary checking in place for the workload profile reference counting, so separate the two. As it is now, we can theoretically end up with the call from begin_use happening while the worker thread is executing which would result in the profile not getting set for that submission. It should not affect the reference counting. v2: bail early if the the profile is already active (Lijo) Reviewed-by:
-
Alex Deucher authored
No need to make the workload profile setup dependent on the results of cancelling the delayed work thread. We have all of the necessary checking in place for the workload profile reference counting, so separate the two. As it is now, we can theoretically end up with the call from begin_use happening while the worker thread is executing which would result in the profile not getting set for that submission. It should not affect the reference counting. v2: bail early if the the profile is already active (Lijo) Reviewed-by:
-
Candice Li authored
Add EEPROM I2C address support for smu v13_0_12. Signed-off-by:
-
Alex Deucher authored
We need to make sure the workload profile ref counts are balanced. This isn't currently the case because we can increment the count on submissions, but the decrement may be delayed as work comes in. Track when we enable the workload profile so the references are balanced. v2: switch to a mutex and active flag v3: fix mutex init Fixes: 1443dd3c ("drm/amd/pm: fix and simplify workload handling") Cc: Yang Wang <kevinyang.wang@amd.com> Cc: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
-
Alex Deucher authored
We need to make sure the workload profile ref counts are balanced. This isn't currently the case because we can increment the count on submissions, but the decrement may be delayed as work comes in. Track when we enable the workload profile so the references are balanced. v2: switch to a mutex and active flag v3: fix mutex init Fixes: 8fdb3958 ("drm/amdgpu/gfx: add ring helpers for setting workload profile") Cc: Yang Wang <kevinyang.wang@amd.com> Cc: Kenneth Feng <kenneth.feng@amd.com> Tested-by:
-
