- Mar 19, 2025
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Kenneth Feng authored
This reverts commit b00fb976. Reason for revert: this causes some tests fail with call trace. Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Acked-by:
Yang Wang <kevinyang.wang@amd.com>
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- Mar 18, 2025
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Alex Deucher authored
We need to make sure the workload profile ref counts are balanced. This isn't currently the case because we can increment the count on submissions, but the decrement may be delayed as work comes in. Track when we enable the workload profile so the references are balanced. v2: switch to a mutex and active flag v3: fix mutex init Fixes: 8fdb3958 ("drm/amdgpu/gfx: add ring helpers for setting workload profile") Cc: Yang Wang <kevinyang.wang@amd.com> Cc: Kenneth Feng <kenneth.feng@amd.com> Tested-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
Kenneth Feng <kenneth.feng@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- Mar 14, 2025
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Alexander Deucher authored
This reverts commit 08c6e5d0. Reason for revert: missing mutex init Change-Id: Iecf610eb82a3c03ca2a854f603b5e7a722f8c264
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Alex Deucher authored
We need to make sure the workload profile ref counts are balanced. This isn't currently the case because we can increment the count on submissions, but the decrement may be delayed as work comes in. Track when we enable the workload profile so the references are balanced. v2: switch to a mutex and active flag Fixes: 8fdb3958 ("drm/amdgpu/gfx: add ring helpers for setting workload profile") Cc: Yang Wang <kevinyang.wang@amd.com> Cc: Kenneth Feng <kenneth.feng@amd.com> Tested-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
Kenneth Feng <kenneth.feng@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Kenneth Feng authored
Shorten the gfx idle worker timeout. This is to sync with DAL when there is no activity on the screen. Original 1 second can not sync with DAL, so DAL can not apply MALL when the workload type is not bootup default. Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
Yang Wang <kevinyang.wang@amd.com>
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- Feb 06, 2025
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Alex Deucher authored
Same as amdgpu_gfx_off_ctrl(), but without the delay for gfxoff disallow. Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Suggested-by:
Błażej Szczygieł <mumei6102@gmail.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- Jan 13, 2025
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Alex Deucher authored
Add helpers to switch the workload profile dynamically when commands are submitted. This allows us to switch to the FULLSCREEN3D or COMPUTE profile when work is submitted. Add a delayed work handler to delay switching out of the selected profile if additional work comes in. This works the same as the VIDEO profile for VCN. This lets dynamically enable workload profiles on the fly and then move back to the default when there is no work. Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- Nov 12, 2024
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Shashank Sharma authored
Currently, the shadow FW space size and alignment information is protected under a flag (adev->gfx.cp_gfx_shadow) which gets set only in case of SRIOV setups. if (amdgpu_sriov_vf(adev)) adev->gfx.cp_gfx_shadow = true; But we need this information for GFX Userqueues, so that user can create these objects while creating userqueue. This patch series creates a method to get this information bypassing the dependency on this check. This patch: - adds a new input parameter flag to the gfx.funcs->get_gfx_shadow_info fptr definition, so that it can accommodate the information without the check (adev->gfx.cp_gfx_shadow) on request. - updates the existing definition of amdgpu_gfx_get_gfx_shadow_info to adjust with this new flag. Next patch in the series is adding a UAPI which will consume this info. V2: split this patch from the new UAPI patch Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian Koenig <christian.koenig@amd.com> Cc: Arvind Yadav <arvind.yadav@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Shashank Sharma <shashank.sharma@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- Nov 08, 2024
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Jie1zhang authored
Add two sysfs interfaces for gfx and compute: gfx_reset_mask compute_reset_mask These interfaces are read-only and show the resets supported by the IP. For example, full adapter reset (mode1/mode2/BACO/etc), soft reset, queue reset, and pipe reset. V2: the sysfs node returns a text string instead of some flags (Christian) v3: add a generic helper which takes the ring as parameter and print the strings in the order they are applied (Christian) check amdgpu_gpu_recovery before creating sysfs file itself, and initialize supported_reset_types in IP version files (Lijo) v4: Fixing uninitialized variables (Tim) Signed-off-by:
Jesse Zhang <Jesse.Zhang@amd.com> Suggested-by:
Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
Tim Huang <tim.huang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- Nov 04, 2024
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lijo lazar authored
Make amdgpu_gfx_sysfs_init/fini functions as common entry points for all gfx related sysfs nodes. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Jie1zhang authored
compute/gfx may have multiple rings on some hardware. In some cases, userspace wants to run jobs on a specific ring for validation purposes. This debugfs entry helps to disable or enable submitting jobs to a specific ring. This entry is populated only if there are at least two or more cores in the gfx/compute ip. Signed-off-by:
Jesse Zhang <jesse.zhang@amd.com> Suggested-by:
Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
Tim Huang <tim.huang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Make sure KFD gets a turn when serializing access to the GC IP. Currently non-KFD jobs can starve KFD if they submit often enough. This patch prevents that by stalling non-KFD if its time period has elapsed. v2: fix units v3: check enablement properly Acked-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- Sep 26, 2024
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Dr. David Alan Gilbert authored
amdgpu_gfx_bit_to_me_queue has been unused since it was added in commit 7470bfcf ("drm/amdgpu: add helper function for gfx queue/bitmap transition") Remove it. Signed-off-by:
Dr. David Alan Gilbert <linux@treblig.org> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- Aug 28, 2024
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Likun Gao authored
Add gc_info table v1.3 for IP discovery. Signed-off-by:
Likun Gao <Likun.Gao@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit 875ff9a7)
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- Aug 23, 2024
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Likun Gao authored
Add gc_info table v1.3 for IP discovery. Signed-off-by:
Likun Gao <Likun.Gao@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- Aug 21, 2024
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SRINIVASAN SHANMUGAM authored
This commit introduces the Enforce Isolation Handler designed to enforce shader isolation on AMD GPUs, which helps to prevent data leakage between different processes. The handler counts the number of emitted fences for each GFX and compute ring. If there are any fences, it schedules the `enforce_isolation_work` to be run after a delay of `GFX_SLICE_PERIOD`. If there are no fences, it signals the Kernel Fusion Driver (KFD) to resume the runqueue. The function is synchronized using the `enforce_isolation_mutex`. This commit also introduces a reference count mechanism (kfd_sch_req_count) to keep track of the number of requests to enable the KFD scheduler. When a request to enable the KFD scheduler is made, the reference count is decremented. When the reference count reaches zero, a delayed work is scheduled to enforce isolation after a delay of GFX_SLICE_PERIOD. When a request to disable the KFD scheduler is made, the function first checks if the reference count is zero. If it is, it cancels the delayed work for enforcing isolation and checks if the KFD scheduler is active. If the KFD scheduler is active, it sends a request to stop the KFD scheduler and sets the KFD scheduler state to inactive. Then, it increments the reference count. The function is synchronized using the kfd_sch_mutex to ensure that the KFD scheduler state and reference count are updated atomically. Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Suggested-by:
Christian König <christian.koenig@amd.com> Suggested-by:
Alex Deucher <alexander.deucher@amd.com>
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SRINIVASAN SHANMUGAM authored
This commit adds a new sysfs attribute 'enforce_isolation' to control the 'enforce_isolation' setting per GPU. The attribute can be read and written, and accepts values 0 (disabled) and 1 (enabled). When 'enforce_isolation' is enabled, reserved VMIDs are allocated for each ring. When it's disabled, the reserved VMIDs are freed. The set function locks a mutex before changing the 'enforce_isolation' flag and the VMIDs, and unlocks it afterwards. This ensures that these operations are atomic and prevents race conditions and other concurrency issues. Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Suggested-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- Aug 16, 2024
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SRINIVASAN SHANMUGAM authored
The cleaner shader is used by the CP firmware to clean LDS and GPRs between processes on the CUs. This adds an internal API for GFX IP code to allocate and initialize the cleaner shader. Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Suggested-by:
Christian König <christian.koenig@amd.com>
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Alex Deucher authored
This will be used in more places in the future so add a mutex. Acked-by:
Vitaly Prosyak <vitaly.prosyak@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Jiadong Zhu authored
Add reset_hw_queue in kiq_pm4_funcs callbacks. Acked-by:
Vitaly Prosyak <vitaly.prosyak@amd.com> Signed-off-by:
Jiadong Zhu <Jiadong.Zhu@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- Jul 23, 2024
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Alex Deucher authored
Add the irq source for bad opcodes. Acked-by:
Felix Kuehling <felix.kuehling@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- Jul 10, 2024
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lijo lazar authored
For SOCs with GFX v9.4.3, a VF may have multiple compute partitions. Fetch the partition information during init and initialize partition nodes. There is no support to switch partition mode in VF mode, hence disable the same. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- Jun 05, 2024
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Sunil khatri authored
Rename the variable ip_dump_cp_queues to ip_dump_compute_queue as it represent compute queues. Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Sunil Khatri <sunil.khatri@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- May 23, 2024
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Sunil khatri authored
Add gfx queue register for all instances in devcoredump for gfx10. Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Sunil Khatri <sunil.khatri@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Sunil khatri authored
Add support to dump registers of all instances of cp queue registers of gfx10 to devcoredump. Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Sunil Khatri <sunil.khatri@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Sunil khatri authored
Rename the memory pointer from ip_dump to ip_dump_core to make it specific to core registers and rest other registers to be dumped in their respective memories. Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Sunil Khatri <sunil.khatri@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- May 13, 2024
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Jie1zhang authored
This code cannot be reached: return "UNKNOWN";. Signed-off-by:
Jesse Zhang <Jesse.Zhang@amd.com> Reviewed-by:
Tim Huang <Tim.Huang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- May 03, 2024
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Sunil khatri authored
reg_count is not used and the register count is directly derived from the array size and hence removed. Signed-off-by:
Sunil Khatri <sunil.khatri@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- Apr 26, 2024
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Sunil khatri authored
Adding gfx10 gc registers to be used for register dump via devcoredump during a gpu reset. Signed-off-by:
Sunil Khatri <sunil.khatri@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- Mar 20, 2024
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Tao Zhou authored
Replace it with related interface in gfxhub functions. v2: replace node id with xcc id. get node id for query_utcl2_poison_status Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- Feb 22, 2024
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majun258 authored
Drop redundant parameters in function amdgpu_gfx_kiq_init_ring to simplify the code Signed-off-by:
Ma Jun <Jun.Ma2@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- Nov 09, 2023
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Victor Lu authored
amdgpu_kiq_wreg/rreg is hardcoded to use MEC engine 0. Add an xcc_id parameter to amdgpu_kiq_wreg/rreg, define W/RREG32_XCC and amdgpu_device_xcc_wreg/rreg to use the new xcc_id parameter. Using amdgpu_sriov_runtime to determine whether to access via kiq or RLC is sufficient for now. v5: add condition in amdgpu_device_xcc_w/rreg, remove trace func call v4: avoid using amdgpu_sriov_w/rreg v3: use W/RREG32_XCC to handle non-kiq case v2: define amdgpu_device_xcc_wreg/rreg instead of changing parameters of amdgpu_device_wreg/rreg Signed-off-by:
Victor Lu <victorchengchi.lu@amd.com> Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- Oct 05, 2023
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lijo lazar authored
Move definition of package type to amdgpu_smuio header and add new package types for CEM and OAM. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- Sep 11, 2023
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Mukul Joshi authored
Currently, we store CU info only for a single XCC assuming that it is the same for all XCCs. However, that may not be true. As a result, store CU info for all XCCs. This info is later used for CU masking. Signed-off-by:
Mukul Joshi <mukul.joshi@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Mukul Joshi authored
Rename KGD_MAX_QUEUES to AMDGPU_MAX_QUEUES to conform with the naming convention followed in amdgpu_gfx.h. No functional change. Signed-off-by:
Mukul Joshi <mukul.joshi@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Mukul Joshi authored
Currently, we store CU info only for a single XCC assuming that it is the same for all XCCs. However, that may not be true. As a result, store CU info for all XCCs. This info is later used for CU masking. Signed-off-by:
Mukul Joshi <mukul.joshi@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- Aug 31, 2023
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lema1 authored
Several new fields are exposed in gc_info v2_1 Signed-off-by:
Le Ma <le.ma@amd.com> Reviewed-by:
Shiwu Zhang <shiwu.zhang@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- Aug 30, 2023
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lema1 authored
Several new fields are exposed in gc_info v2_1 Signed-off-by:
Le Ma <le.ma@amd.com> Reviewed-by:
Shiwu Zhang <shiwu.zhang@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- Jun 30, 2023
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Alex Deucher authored
So we can selectively enable it on certain devices. No intended functional change. Reviewed-and-tested-by:
Jiadong Zhu <Jiadong.Zhu@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- Jun 09, 2023
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Tao Zhou authored
Add common GFX RAS definitions. v2: remove instance from amdgpu_gfx_ras_reg_entry, amdgpu_ras_err_status_reg_entry has already defined it. v3: remove memory id definitions from amdgpu_gfx.h, they are related to IP version. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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