- May 15, 2024
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These currently only work because we have a redirection set up; let's link to the right place instead. Part-of: <mesa/mesa!29224>
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Drivers might still be busy doing things and not properly clean things up. Fixes a rare crash on applicatione exits with some drivers. Fixes: 50e981a0 ("rusticl/mesa: add fencing support") Part-of: <mesa/mesa!29223>
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Miptails are now disabled on Tile64 resources, so we can drop this restriction. Ref: e3a5ade9 ('intel/isl: Disable miptails to align LODs for CCS WA') This reverts commit 8670fd6a. Reviewed-by:
Nanley Chery <nanley.g.chery@intel.com> Part-of: <mesa/mesa!28984>
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Part-of: <mesa/mesa!29201>
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and improve comment Part-of: <mesa/mesa!29201>
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Part-of: <mesa/mesa!29201>
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Part-of: <mesa/mesa!29201>
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Part-of: <mesa/mesa!29201>
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Part-of: <mesa/mesa!29201>
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Part-of: <mesa/mesa!29201>
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It's already set higher up in that same file. Part-of: <mesa/mesa!29201>
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Unused since 1eca8096 ("ci/v3dv: test v3dv in arm64 environment"), and in the meantime other code paths have been added and do not support this (`.gitlab-ci/common/init-stage2.sh` when starting xorg & wayland for instance), so instead of fixing dead code, let's remove it. Part-of: <mesa/mesa!29201>
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Allows for tighter timeouts. Part-of: <mesa/mesa!29201>
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More verbose, sure, but also much easier to understand. Part-of: <mesa/mesa!29201>
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More verbose, sure, but also much easier to understand. Part-of: <mesa/mesa!29201>
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Instead of inheriting from the build job in the test job; it makes no sense to tie them like this. Part-of: <mesa/mesa!29201>
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Part-of: <mesa/mesa!29201>
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The name was way too generic, and the next commit introduces an actual `.debian-container` dot-job. Part-of: <mesa/mesa!29201>
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2712D0 has V3D 7.1.10 which included draw index and base vertex in the shader state record packet, shuffling the locations of most of its fields. Handle this at run time by emitting the appropriate packet based on the V3D version since our current versioning framework doesn't support changes based on revision number alone. Part-of: <mesa/mesa!29189>
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2710D0 has V3D 7.1.10 which included draw index and base vertex in the shader state record packet, shuffling the locations of most of its fields. Handle this at run time by emitting the appropriate packet based on the V3D version since our current versoning framework doesn't support changes based on revision number alone. Part-of: <mesa/mesa!29189>
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Part-of: <mesa/mesa!29189>
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Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by:
Ivan Briano <ivan.briano@intel.com> Part-of: <mesa/mesa!25814>
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Reviewed-by:
Ivan Briano <ivan.briano@intel.com> Part-of: <mesa/mesa!25814>
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Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by:
Ivan Briano <ivan.briano@intel.com> Part-of: <!25814>
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Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by:
Ivan Briano <ivan.briano@intel.com> Part-of: <mesa/mesa!25814>
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So that the driver can decode the printf buffer. We're not going to use the NIR data directly from the driver (Iris/Anv) because the late compile steps might want to add more printfs. Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by:
Ivan Briano <ivan.briano@intel.com> Part-of: <mesa/mesa!25814>
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We'll use the delta for an upcoming internal printf mechanism, where the PARAM_IDX will be the base printf reloc identifier and the BASE will be the string id. Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by:
Ivan Briano <ivan.briano@intel.com> Part-of: <mesa/mesa!25814>
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Reviewed-by:
Ivan Briano <ivan.briano@intel.com> Part-of: <mesa/mesa!25814>
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Uses the same memory layout as the print intrinsic lowering. This one just let's you do the emission without having to deal with variables. This useful for debug traces. Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by:
Karol Herbst <kherbst@redhat.com> Reviewed-by:
Ivan Briano <ivan.briano@intel.com> Part-of: <mesa/mesa!25814>
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Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by:
Karol Herbst <kherbst@redhat.com> Reviewed-by:
Ivan Briano <ivan.briano@intel.com> Part-of: <mesa/mesa!25814>
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This will allow a driver to use a single table of printf strings across all shaders. Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by:
Karol Herbst <kherbst@redhat.com> Reviewed-by:
Ivan Briano <ivan.briano@intel.com> Part-of: <mesa/mesa!25814>
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Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: mesa-stable Reviewed-by:
Karol Herbst <kherbst@redhat.com> Reviewed-by:
Ivan Briano <ivan.briano@intel.com> Part-of: <mesa/mesa!25814>
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Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes: 7c76125d ("anv: use 2 different buffers for surfaces/samplers in descriptor sets") Reviewed-by:
Ivan Briano <ivan.briano@intel.com> Part-of: <mesa/mesa!25814>
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It is based on Adreno 740, with difference in SP_UNKNOWN_AE09 and TPL1_DBG_ECO_CNTL1. We also enable cmdbuf_start_a725_quirk since blob does the same. Values taken from blob v744.19 Signed-off-by:
Danylo Piliaiev <dpiliaiev@igalia.com> Part-of: <mesa/mesa!29087>
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All the non-transpose messages are SIMD 1,2,4,8,16,32 capable (BSpec 57330) Signed-off-by:
Rohan Garg <rohan.garg@intel.com> Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <mesa/mesa!29212>
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To match other helpers. Signed-off-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <!29192>
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It's exactly the same as radeon_set_uconfig_reg_perfctr(). Signed-off-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <mesa/mesa!29192>
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This is the base helper for emitting packets, it will be much more closer to the new command buffer recording mecanishm if we decide to use the same helpers as RadeonSI. Signed-off-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <mesa/mesa!29192>
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It will be easier to share helpers between RadeonSI and RADV. Signed-off-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <mesa/mesa!29192>
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Part-of: <mesa/mesa!29205>
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