- Oct 13, 2021
-
-
Eric Engestrom authored
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
-
Kenneth Graunke authored
Apparently, we've been requiring a 4K alignment for internally allocated clear color addresses to work around some unknown issues. There's a comment to that effect in iris_resource_create_with_modifiers(). When importing a dmabuf and tacking on an additional clear color BO, we only required an alignment of 1. This wasn't a problem for a long time because all BO allocations were naturally aligned to the 4K page size. However, once we enabled suballocation, we were able to allocate "BOs" at 256B granularity, making this no longer 4K aligned. Increase the alignment requirement to 4K to match the behavior of our normal allocations and also our previous behavior. Fixes Piglit's ext_image_dma_buf_import-intel-modifiers. Closes: mesa/mesa#5482 Fixes: ce2e2296 ("iris: Suballocate BO using the Gallium pb_slab mechanism") Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Nanley Chery <nanley.g.chery@intel.com> Part-of: <mesa/mesa!13326>
-
Caio Oliveira authored
Reviewed-by: Matt Turner <mattst88@gmail.com> Part-of: <mesa/mesa!13340>
-
Caio Oliveira authored
Be consistent with the other test suites in intel/compiler. Reviewed-by: Matt Turner <mattst88@gmail.com> Part-of: <mesa/mesa!13340>
-
Mike Blumenkrantz authored
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <mesa/mesa!13320>
-
Mike Blumenkrantz authored
unnecessarily dereferencing the vertex buffer info array here causes a ton of cpu overhead due to bad cache locality, so just use a mask to avoid loading X more cachelines into memory unnecessarily Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <mesa/mesa!13320>
-
Mike Blumenkrantz authored
when the shader pipeline is known to not require any of the more complex calculations, those calculations can be excluded from the dynamic update code Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <mesa/mesa!13320>
-
Mike Blumenkrantz authored
this avoids incurring overhead at draw time, instead shifting it to vertex binding commands Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <mesa/mesa!13320>
-
Mike Blumenkrantz authored
NULL here means this was regular CmdBindVertexBuffers, so the stride cannot be used Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <mesa/mesa!13320>
-
Adam Jackson authored
Why is this not the same code as EGL_MESA_platform_surfaceless. Reviewed-by: Emma Anholt <emma@anholt.net> Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com> Part-of: <mesa/mesa!13182>
-
Adam Jackson authored
There's no danger of accidentally using these, the default pixel format is integer and if you want float you need to have explicitly asked for it in eglChooseConfig. Reviewed-by: Emma Anholt <emma@anholt.net> Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com> Part-of: <mesa/mesa!13182>
-
Adam Jackson authored
Since we're not checking for this, xcb has to do it for us the first time we call xcb_sync_destroy_fence, which puts a blocking round-trip in the swapchain destroy path for no reason. Check for the extension so we have the extension's opcode cached when we need it. Reviewed-by: Michel Dänzer <mdaenzer@redhat.com> Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com> Part-of: <mesa/mesa!13339>
-
Lone_Wolf authored
Reviewed-by: Karol Herbst <kherbst@redhat.com> Part-of: <mesa/mesa!13290>
-
Emma Anholt authored
This reverts commit 90faabc0. It has been flaky and producing timeouts. (See https://gitlab.freedesktop.org/mesa/mesa/-/jobs/14634204 for an example) Acked-by: Jesse Natalie <jenatali@microsoft.com> Part-of: <!13318>
-
Lionel Landwerlin authored
If the ISL caller didn't specify a row_pitch_B, let's use the NVIDIA/AMD requirements. Otherwise keep using the Intel requirement, as the caller is likely trying to import a buffer and if we can deal with that row_pitch_B, we should accept it. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes: a3a4517f ("isl: Work around NVIDIA and AMD display pitch requirements") Reported-by: Dongwon Kim <dongwon.kim@intel.com> Reviewed-by: Nanley Chery <nanley.g.chery@intel.com> Part-of: <mesa/mesa!13024>
-
Lionel Landwerlin authored
Small typo/copy-paste. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes: c0093c46 ("anv: Flip around the way we reason about storage image lowering") Reviewed-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <mesa/mesa!13332>
-
Bas Nieuwenhuizen authored
Only try to invalidate L2 if we actually hit one of the incoherent images. Note we may actually insert some extra flushes at the end of a command buffer so that we may asume the caches are clean the start of the next command buffer. However, on average I think that case is uncommon enough that being able to make assumptions at the start of a cmdbuffer is beneficial. Especially since MSAA is somewhat rare in more recent games. Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <mesa/mesa!13239>
-
Bas Nieuwenhuizen authored
So that we can mark the rendertargets dirty. Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <!13239>
-
Bas Nieuwenhuizen authored
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <mesa/mesa!13239>
-
Hyunjun Ko authored
Now we can enable strictLines as we set rectangular lines by default. Signed-off-by: Hyunjun Ko <zzoon@igalia.com> Part-of: <mesa/mesa!6020>
-
Hyunjun Ko authored
By default line mode is VK_LINE_RASTERIZATION_MODE_RECTANGULAR_EXT, when lineRasterizationMode is VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT and primtype is line - we enable bresenham line mode. We have to disable MSAA when bresenham lines are used, this is a hardware limitation and spec allows it: "When Bresenham lines are being rasterized, sample locations may all be treated as being at the pixel center (this may affect attribute and depth interpolation)." This forces us to re-emit msaa state when line mode is changed. Signed-off-by: Hyunjun Ko <zzoon@igalia.com> Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com> Part-of: <!6020>
-
Hyunjun Ko authored
This bit seems like the control for line mode of rastrization. That can be simply figured out by comparing dEQP-VK.rasterization.primitives.no_stipple.bresenham_lines, dEQP-VK.rasterization.primitives.no_stipple.rectangular_lines and dEQP-VK.rasterization.primitives.no_stipple.lines. For opengl, the value of bresenham lines mode, which is 0, is set by default and the value of rectangular mode, which is 0x1, is set when multi-sampled. For vulkan, the bresenham lines are enabled when lineRasterizationMode is VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT, which sets the bit to 0, while the value is 1 when it's VK_LINE_RASTERIZATION_MODE_RECTANGULAR_EXT, that seems to be default. If both multi-sampled and bresenham-lines are used when primitive type is line, the bit is to be set as 0 and makes msaa disabled. Note that this is only tested on a6xx, but I guess it's likely the same for a5xx. Signed-off-by: Hyunjun Ko <zzoon@igalia.com> Part-of: <mesa/mesa!6020>
-
Tapani Pälli authored
Otherwise we hit assert in vk_object_base_assert_valid when attemping to create handle from anv_fence with unknown base type. Cc: mesa-stable Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <mesa/mesa!13330>
-
Emma Anholt authored
A refactor dropped one of the frees. Fixes: 380ac288 ("ac: import performance counters from RadeonSI") Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <mesa/mesa!13322>
-
Yipeng Chen (Jasber) authored
This is to fix serious performance drop of texture_upload/ texture_resue relative items in chromeos glbench test. Staging texture is not efficient for CPU uploading. Signed-off-by: Jasber Chen <yipeng.chen@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <mesa/mesa!13306>
-
Marek Olšák authored
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <mesa/mesa!12789>
-
Marek Olšák authored
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <mesa/mesa!12789>
-
Arvind Yadav authored
This patch is to to remove PKT3_CONTEXT_REG_RMW from radeonsi. and avoid multiple command buffer(PM4 packet)creation for R_02881C_PA_CL_VS_OUT_CNTL. Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Signed-off-by: Arvind Yadav <arvind.yadav@amd.com> Part-of: <mesa/mesa!12789>
-
Timur Kristóf authored
Cc: mesa-stable Closes: mesa/mesa#5433 Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <mesa/mesa!13312>
-
Timur Kristóf authored
Cc: mesa-stable Closes: mesa/mesa#5071 Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <mesa/mesa!13312>
-
Timur Kristóf authored
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <mesa/mesa!13312>
-
Marek Olšák authored
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <mesa/mesa!13214>
-
Marek Olšák authored
Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <mesa/mesa!13214>
-
Marek Olšák authored
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <mesa/mesa!13214>
-
Tapani Pälli authored
Common queue submit expects pWaitDstStageMask to be set per each semaphore (as per Vulkan spec) and crashes if these are not given properly. This fixes crashes seen when running vulkan apps on Android. v2: change the VkPipelineStageFlags given (Lionel) Fixes: b996fa8e ("anv: implement VK_KHR_synchronization2") Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <mesa/mesa!13305>
-
Kyle Brenneman authored
eglFunctionList.py isn't executed directly, so it doesn't need a shebang line. Part-of: <mesa/mesa!13130>
-
Kyle Brenneman authored
A few of the GLVND-related files were missing a copyright comment at the top. Copy the same MIT license text from gen_egl_dispatch.py et. al. mesa/mesa#5267 Part-of: <mesa/mesa!13130>
-
Rhys Perry authored
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com> Tested-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com> Closes: mesa/mesa#4768 Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <mesa/mesa!11717>
-
Rhys Perry authored
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <mesa/mesa!11717>
-
Rhys Perry authored
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <mesa/mesa!11717>
-