-
drm-intel-fixes-2019-10-10e137d3ab · ·
- Fix CML display by adding a missing ID. - Drop redundant list_del_init - Only enqueue already completed requests to avoid races - Fixup preempt-to-busy vs reset of a virtual request - Protect peeking at execlists->active - execlists->active is serialised by the tasklet drm-intel-next-fixes-2019-09-19: - Extend old HSW workaround to fix some GPU hangs on Haswell GT2 - Fix return error code on GEM mmap. - White list a chicken bit register for push constants legacy mode on Mesa - Fix resume issue related to GGTT restore - Remove incorrect BUG_ON on execlist's schedule-out - Fix unrecoverable GPU hangs with Vulkan compute workloads on SKL drm-intel-next-fixes-2019-09-26: - Fix concurrence on cases where requests where getting retired at same time as resubmitted to HW - Fix gen9 display resolutions by setting the right max plane width - Fix GPU hang on preemption - Mark contents as dirty on a write fault. This was breaking cursor sprite with dumb buffers.
-
drm-intel-next-2019-10-079445ad17 · ·
UAPI Changes: - Never allow userptr into the mappable GGTT (Chris) No existing users. Avoid anyone from even trying to spare a deadlock scenario. Cross-subsystem Changes: Core Changes: Driver Changes: - Eliminate struct_mutex use as BKL! (Chris) Only used for execbuf serialisation. - Initialize DDI TC and TBT ports (D-I) on Tigerlake (Lucas) - Fix DKL link training for 2.7GHz and 1.62GHz (Jose) - Add Tigerlake DKL PHY programming sequences (Clinton) - Add Tigerlake Thunderbolt PLL divider values (Imre) - drm/i915: Use helpers for drm_mm_node booleans (Chris) - Restrict L3 remapping sysfs interface to dwords (Chris) - Fix audio power up sequence for gen10+ display (Kai) - Skip redundant execlist resubmission (Chris) - Only unwedge if we can reset GPU first (Chris) - Initialise breadcrumb lists on the virtual engine (Chris) - Don't rely on kernel context existing during early errors (Matt A) - Update Icelake+ MG_DP_MODE programming table (Clinton) - Update DMC firmware for Icelake (Anusha) - Downgrade DP MST error after unplugging TypeC cable (Srinivasan) - Limit MST modes based on plane size too (Ville) - Polish intel_tv_mode_valid() (Ville) - Fix g4x sprite scaling stride check with GTT remapping (Ville) - Don't advertize non-exisiting crtcs (Ville) - Clean up encoder->crtc_mask setup (Ville) - Use tc_port instead of port parameter to MG registers (Jose) - Remove static variable for aux last status (Jani) - Implement a better i945gm vblank irq vs. C-states workaround (Ville) - Make the object creation interface consistent (CQ) - Rename intel_vga_msr_write() to intel_vga_reset_io_mem() (Jani, Ville) - Eliminate previous drm_dbg/drm_err usage (Jani) - Move gmbus setup down to intel_modeset_init() (Jani) - Abstract all vgaarb access to intel_vga.[ch] (Jani) - Split out i915_switcheroo.[ch] from i915_drv.c (Jani) - Use intel_gt in has_reset* (Chris) - Eliminate return value for i915_gem_init_early (Matt A) - Selftest improvements (Chris) - Update HuC firmware header version number format (Daniele)
-
drm-intel-fixes-2019-10-03-1485f682b · ·
- Fix DP-MST crtc_mask - Fix dsc dpp calculations - Fix g4x sprite scaling stride check with GTT remapping Short summary of fixes pull (less than what git shortlog provides): - explain anything non-fixes (e.g. cleanups) and why it's appropriate - highlight regressions - summarize pull requests contained This shouldn't be more than a few lines (or it indicates your fixes pull is a bit too big).
-
drm-intel-fixes-2019-10-03eb0192fe · ·
- Fix dsc dpp calculations - Fix g4x sprite scaling stride check with GTT remapping
-
drm-intel-next-2019-09-279cd6c339 · ·
UAPI Changes: - Revert "drm/i915: Fix DP-MST crtc_mask" to avoid MST regressions (Ville) - Disable set/get_tiling ioctl on Gen12+ as hardware is gone (Daniel) - Add immutable zpos plane properties (Ville) - Report dual-subslice count as subslices for Tigerlake (Daniele) Driver Changes: <TIGERLAKE ENABLING> - Enable HDCP 1.4 and 2.2 on Gen12+ (Ramalingam) - Enable display state buffer (DSB) batch-programming (Animesh) - Add 12 BPC support for Tigerlake (Anusha) - Add maximum resolution supported by PSR2 HW for Tigerlake (Jose) - Only allow PSR2 on supporting transcoders (Jose) - Disable pipes in reverse order to comply with MST for Tigerlake+ (Jose) - Implement Tigerlake DisplayPort training sequence (Jose) - Do not apply WaIncreaseDefaultTLBEntries from Gen12 onwards (Michel) - Reuse Icelake OA context logic for Tigerlake (Michel) - Enable VD HCP/MFX sub-pipe power gating (Michel) - Use separate context for relocations to deal with Tigerlake pre-parser (Daniele) - Enabling DSC on Pipe A for Tigerlake (Madhumitha) - Remove Yf tiling and legacy CCS support starting Tigerlake (Dhinakaran) - Remove PSR link standby support starting Tigerlake (Jose) - Access the right register when handling PSR interruptions (Jose) - Move DP_TP_* registers from port to transcoder for Tigerlake (Lucas) - Disable SAGV for Tigerlake (Lucas) - Reuse Gen11 stolen initialization for Gen12 (Lucas) - Apply FBC WA for Tigerlake too (Jose) - Use engine relative LRIs on context setup for Tigerlake (Mika, Daniele) - Register state context definition for Gen12 (Michel) - Extend MI_SEMAPHORE_WAIT instruction for Tigerlake (Chris) - Disable various Tigerlake features in attempt to have stable CI results (Chris) - Add Tigerlake W/A to disable CPS aware color pipe by setting chicken bit (Radhakrishna) - Add Tigerlake W/A to Enable Small PL for power benefit (Michel) - Add missing DDI clock select during DP init sequence for Tigerlake (Clinton) - Add missing update_active_dpll callback on Tigerlake (Clinton) - Finish modular FIA support on registers for Tigerlake (Jose) - Unify disable and enable phy clock gating functions on Tigerlake (Jose) - Check the UC health of TC controllers after power on (Jose) - Add TigerLake bandwidth checking (Stanislav) - Add Pipe D cursor ctrl register for Gen12 (Ankit) - Add DKL PHY PLL calculations (Lucas, Vandita, Jose) - Add memory type decoding for bandwidth checking (James) </TIGERLAKE ENABLING> - Downgrade Gen7 and Cherryview back to aliasing-ppGTT (Chris) - Limit MST to <= 8bpc once again (Ville) - Restrict the aliasing-ppgtt to the size of the ggtt (Chris) - Restore relaxed padding (OCL_OOB_SUPPRES_ENABLE) for SKL+ (Chris, Jason) - Whitelist COMMON_SLICE_CHICKEN2 (Kenneth) - Include GTT page-size info in error state (Matt A) - Clear STOP_RING bit on reset (Chris) - Ignore lost CSB completion events (Chris) - Use a high priority wq for nonblocking plane updates (Ville) - Bump up Skylake/Icelake+ display/plane/fb size restrictions (Manasi, Ville) - Update Gen11/Gen12 forcewake ranges from BSpec (Mika, Daniele, Michel) - Allow downscale factor of <3.0 on GLK+ for all formats (Ville) - Add missing Comet Lake PCH PCI ID (Matt) - Fix Gen11 SFC reset flow (Daniele) - Fix YCbCr programming for ILK-IVB,HSW+ (Ville) - Save audio frequency programming state at audio domain suspend (Kai) - Fix DisplayPort DSC BPP calculations (Maarten) - Add hardware readout for FEC (Maarten) - Do not add all planes when checking scalers on GLK+ (Maarten) - Make small joiner RAM buffer size platform-specific (Matt R) - Use per-process HWSP as scratch (Michal Wi) - Match allowed Gen11+ CDCLK values to BSpec (Matt R) - Rework CDCLK code for clarity and table format (Matt R) - Unify CDCLK code to reuse functions (Ville) - Enhance CDCLK sanitization (Matt R) - Preallocate Braswell top-level page directory (Chris) - Make vgpu ppgtt notificaiton as atomic operation (Xiaolin) - Use NOEVICT for first pass on attemping to pin a GGTT mmap (Chris) - Disable PSR if more than one eDP panel is present (Jose) - Make breadcrumb flushes more robust (Chris) - Extend non readable MCR range (Mika) - Protect our local workers against I915_FENCE_TIMEOUT (Chris) - Allow stolen memory (and future local memory) addresses in sg_table (Matt A) - Better organize the disable sequence in atomic_commit_tail() (Manasi) - Fix regression with crtc disable ordering (Maarten) - Add HW Gamma LUT readout (Swati) - Hook up power management code to use intel_gt (Andi) - Rework codebase towards use of intel_gt (Tvrtko) - Remove incorrect BUG_ON for schedule-out (Chris, Vinay) - Cleanup cache coloring code (Matt A) - Flush writes before RING_TAIL update on SNB (Chris) - Perform GGTT restore much earlier during resume (Chris) - Make shrink pinning atomic (Chris) - Make i915_vma.flags atomic for mutex reduction (Chris) - Make sure the gen6 ppgtt is bound before first use without struct mutex (Chris) - Report IOMMU status in debugfs (Chris) - Disable FBC if BIOS reserved memory (stolen) is unavailable (Chris) - Add a paranoid flushes and context reload around GPU reset (Chris) - Skip engine busyness sampling when and where not needed (Tvrtko) - Use GT parked time for estimating RC6 while asleep (Chris) - Get the correct wakeref for reading hotplug registers from debugfs (Arkadiusz) - Only apply a rmw mmio update if the value changes (Chris, Daniele) - Extend Haswell GT1 PSMI workaround to all HSW (Chris) - Only enqueue already completed requests (Chris) - Fix preempt-to-busy interactions of virtual requests (Chris) - Prevent bonded requests from overtaking each other on preemption (Chris) - Mark contents as dirty on a write fault (Chris) - Adjust length of MI_LOAD_REGISTER_REG (Michal Wi) - Don't disable interrupts for intel_engine_breadcrumbs_irq() (Sebastian) - Extract GT render sleep (rc6) management (Andi) - Rework SSEU reporting code (Stuart) - Use correct DSC registers in intel_configure_pps_for_dsc_encoder (Manasi) - Use enum pipe instead of crtc index to track active pipes (Ville) - Enforce irq-off lockdep check for for timeline locks (Chris) - Flush the existing fence before GGTT read/write (Chris) - Keep drm_i915_file_private around under RCU (Chris) - Call dma_set_max_seg_size() to silence spurious warnings (Lyude) - Make engine's batch pool safe for use with virtual engines (Chris) - Align power domain names with port names (Imre) - Parameterize and unify HPD code (Lucas) - Use RCU for unlocked vm_idr lookup (Chris) - Replace obj->pin_global with obj->frontbuffer (Chris) - Rework code to use INTEL_NUM_PIPES() (Jani) - Convert device info num_pipes to pipe_mask (Jani) - Introduce INTEL_DISPLAY_ENABLED() (Jani) - Stop conflating HAS_DISPLAY() and disabled display (Jani) - Modularize i915 modesetting probing/init code (Jani) - Use drm_format_info_is_yuv_semiplanar() instead of rolling own (Ville) - Other display codebase cleanups (Ville) - Other GEM codebase cleanup, lockdep and selftest improvements (Chris) - Future-proof DDC pin mapping to reuse ICP variant (Matt R) - Rewrite timeline handling to be RCU based (Chris) - Define explicit wedged on init reset state (Michal Wi) - Add GuC firmware for Elkhartlake (Daniele) - Update HuC firmware naming convention and bump versions (Anusha) - Extract common code from GuC stop/disable comm (Fernando) - Fix perf kernel-doc formatting for struct members (Anna) - Documentation fixes (Joonas)
-
drm-intel-next-fixes-2019-09-26458863e0 · ·
- Fix concurrence on requests that were getting retired while resubmission - Fix supported display resolution on gen9 patform by using right plane width. - Prevent GPU hang on preemption - Fix cursor sprites by marking contents as dirty on a write fault
-
drm-intel-next-fixes-2019-09-19a95819a1 · ·
- Extend old HSW workaround to fix some GPU hangs on Haswell GT2 - Fix return error code on GEM mmap. - White list a chicken bit register for push constants legacy mode on Mesa - Fix resume issue related to GGTT restore - Remove incorrect BUG_ON on execlist's schedule-out - Fix unrecoverable GPU hangs with Vulkan compute workloads on SKL
-
drm-intel-next-fixes-2019-09-18a95819a1 · ·
- Extend old HSW workaround to fix some GPU hangs on Haswell GT2 - Fix return error code on GEM mmap. - White list a chicken bit register for push constants legacy mode on Mesa - Fix resume issue related to GGTT restore - Remove incorrect BUG_ON on execlist's schedule-out - Fix unrecoverable GPU hangs with Vulkan compute workloads on SKL
-
drm-intel-next-fixes-2019-09-116e5c5272 · ·
Few fixes on GGTT and PPGTT around pin, locks, fence and vgpu. This also includes GVT fixes with two recent fixes: one for recent guest hang regression and another for guest reset fix.
-
drm-intel-fixes-2019-09-112eb0964e · ·
Final drm/i915 fixes for v5.3: - Fox DP MST high color depth regression - Fix GPU hangs on Vulkan compute workloads
-
drm-intel-fixes-2019-08-2932f0a982 · ·
drm/i915 fixes for v5.3-rc7: - Fix DP MST max BPC property creation after DRM register - Fix unused ggtt deballooning and NULL dereference in guest - Fix DSC eDP transcoder identification - Fix WARN from DMA API debug by setting DMA max segment size
-
drm-intel-next-2019-08-22be91233b · ·
- More TGL enabling work (Michel, Jose, Lucas) - Fixes on DP MST (Ville) - More GTT and Execlists fixes and improvements (Chris) - Code style clean-up on hdmi and dp side (Jani) - Fix null pointer dereferrence (Xiong) - Fix a couple of missing serialization on selftests (Chris) - More vm locking rework (Chris)
-
drm-intel-fixes-2019-08-22ed19e303 · ·
drm/i915 fixes for v5.3-rc6: - fix hardware state readout for 10 bpc HDMI
-
drm-intel-next-2019-08-20d70898e4 · ·
- GuC and HuC related fixes and improvements (Daniele, Michal) - Improve debug with more engine information and rework on debugfs files (Chris, Stuart) - Simplify appearture address handling (Chris) - Other fixes and cleanups around engines and execlists (Chris) - Selftests fixes (Matt, Chris) - Gen11 cache flush related fixes and improvements (Mika) - More work around requests, timelines and locks to allow removal of struct_mutex (Chris) - Add missing CML PCI ID (Anusha) - More work on the new i915 buddy allocator (Matt) - More headers, files and directories reorg (Daniele) - Improvements on ggtt’s get pdp (Mika) - Fix GPU reset (Chris) - Fix GPIO pins on gen11 (Matt) - Fix HW readout for crtc_clock in HDMI mode (Imre) - Sanitize display Phy during unitit to workaround messages of HW state change during suspend (Imre) - Be defensive when starting vma activity (Chris) - More Tiger Lake enabling work (Michel, Daniele, Lucas) - Relax pd_used assertion (Chris)
-
drm-intel-fixes-2019-08-15
drm/i915 fixes for v5.4-rc5: - GVT use-after-free fix
-
drm-intel-next-2019-08-13be6133b8 · ·
- More Tiger Lake enabling work (Lucas, Jose, Tomasz, Michel, Jordan, Anusha, Vandita) - More selftest organization reworks, fixes and improvements (Lucas, Chris) - Simplifications on GEM code like context and cleanup_early (Chris, Daniele) - GuC and HuC related fixes and improvements (Daniele, Michal, Chris) - Some clean up and fixes on headers, Makefile, and generated files (Lucas, Jani) - MOCS setup clean up (Tvrtko) - More Elkhartlake enabling work (Jose, Matt) - Fix engine reset by clearing in flight execlists requests (Chris) - Fix possible memory leak on intel_hdcp_auth_downstream (Wei) - Introduce intel_gt_runtime_suspend/resume (Daniele) - PMU improvements (Tvrtko) - Flush extra hard after writing relocations through the GTT (Chris) - Documentations fixes (Michal, Chris) - Report dma_reserv allocation failure (Chris) - Improvements around shrinker (Chris) - More improvements around engine handling (Chris) - Also more s/dev_priv/i915 (Chris) - Abstract display suspend/resume operations (Rodrigo/Jani) - Drop VM_IO from GTT mappings (Chris) - Fix some NULL vs IS_ERR conditions (Dan) - General improvements on error state (Chris) - Isolate i915_getparam_iocrtl to its own file (Chris) - Perf OA object refactor (Umesh) - Ignore central i915->kernel_context and allocate it directly (Chris) - More fixes and improvements around wakerefs (Chris) - Clean-up and improvements around debugfs (Chris) - Free the imported shmemfs file for phys objects (Chris) - Many other fix and cleanups around engines and execlists (Chris) - Split out uncore_mmio_debug (Daniele) - Memory management fixes for blk and gtt (Matt) - Introduction of buddy allocator to handle huge-pages for GTT (Matt) - Fix ICL and TGL PG3 power domains (Anshuman) - Extract GT IRQ to gt/ (Andi) - Drop last_fence tracking in favor of whole vma->active (Chris) - Make overlay to use i915_active instead of i915_active_request (Chris) - Move misc display IRQ handling to its own function (Jose) - Introduce new _TRANS2() macro in preparation for some coming PSR related work (Jose) This tag also includes Gvt stuff including several enhancements for command parser and batch buffer shadow, remove extra debugfs function return check, and other misc changes like typo, static check fix, etc.
-
drm-intel-fixes-2019-08-0873a0ff0b · ·
drm/i915 fixes for v5.3-rc4: - Fix GLK DSI escape clock setting - Fix a memleak on HDCP revoked Ksv error path
-
drm-intel-fixes-2019-08-024b9bb972 · ·
drm/i915 fixes for v5.3-rc3: - GVT fixes - Fix TBT aux powerwell - Fix PSR2 training pattern duration - Fix memory leak in runtime wakeref tracking - Fix ICL memory bandwidth issue preventing planes from being enabled - Fix OA mux configuration delays for accurate performance data - Fix VLV/CHV DP audio cdclk frequency requirements - Fix register whitelisting to fix a number of GL & Vulkan CTS tests - Fix ICL perf register offsets - Fix Gen11 Sampler Prefetch workaround, impacting dEQP tests - Fix various gen2 tracepoints - A number of GEM locking fixes addressing lockdep issues - Fix idle engine reset, recover only active engines - Fix incorrect MCR programming
-
drm-intel-next-2019-07-30e0e712fe · ·
- More changes on simplifying locking mechanisms (Chris) - Selftests fixes and improvements (Chris) - More work around engine tracking for better handling (Chris, Tvrtko) - HDCP debug and info improvements (Ram, Ashuman) - Add DSI properties (Vandita) - Rework on sdvo support for better debuggability before fixing bugs (Ville) - Display PLLs fixes and improvements, specially targeting Ice Lake (Imre, Matt, Ville) - Perf fixes and improvements (Lionel) - Enumerate scratch buffers (Lionel) - Add infra to hold off preemption on a request (Lionel) - Ice Lake color space fixes (Uma) - Type-C fixes and improvements (Lucas) - Fix and improvements around workarounds (Chris, John, Tvrtko) - GuC related fixes and improvements (Chris, Daniele, Michal, Tvrtko) - Fix on VLV/CHV display power domain (Ville) - Improvements around Watermark (Ville) - Favor intel_ types on intel_atomic functions (Ville) - Don’t pass stack garbage to pcode (Ville) - Improve display tracepoints (Steven) - Don’t overestimate 4:2:0 link symbol clock (Ville) - Add support for 4th pipe and transcoder (Lucas) - Introduce initial support for Tiger Lake platform (Daniele, Lucas, Mahesh, Jose, Imre, Mika, Vandita, Rodrigo, Michel) - PPGTT allocation simplification (Chris) - Standardize function names and suffixes to make clean, symmetric and let checkpatch happy (Janusz) - Skip SINK_COUNT read on CH7511 (Ville) - Fix on kernel documentation (Chris, Michal) - Add modular FIA (Anusha, Lucas) - Fix EHL display (Matt, Vivek) - Enable hotplug retry (Imre, Jose) - Disable preemption under GVT (Chris) - OA; Reconfigure context on the fly (Chris) - Fixes and improvements around engine reset. (Chris) - Small clean up on display pipe fault mask (Ville) - Make sure cdclk is high enough for DP audio on VLV/CHV (Ville) - Drop some wmb() and improve pwrite flush (Chris) - Fix critical PSR regression (DK) - Remove unused variables (YueHaibing) - Use dev_get_drvdata for simplification (Chunhong) - Use upstream version of header tests (Jani)
-
drm-intel-fixes-2019-07-10d7e8a19b · ·
- Userptr/ext4 interplay WARN fix (https://bugzilla.kernel.org/show_bug.cgi?id=203317) - Fix a regression on saturated media transcoding system - Invalid pointer deref fix in error capture (triggered by hang) - Missing Icelake W/As