- Feb 25, 2023
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now that the mem type is passed directly to pb, there have to be enough slabs to allocate all the mem types (not heaps), so create memoryTypeCount slabs to allow this fixes #8369 Fixes: f6d3a575 ("zink: zink_heap isn't 1-to-1 with memoryTypeIndex" Part-of: <mesa/mesa!21526>
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- Feb 24, 2023
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Indeed, buffer_in_ram could be reallocated by fixup_vertex() which triggers this issue. For instance, with "piglit/gl-1.0-dlist-materials -auto -fbo": ==28392==ERROR: AddressSanitizer: heap-use-after-free on address 0x607000010024 at pc 0x7f3f416fcf18 bp 0x7f3f33d12800 sp 0x7f3f33d127f8 WRITE of size 4 at 0x607000010024 thread T6 #0 0x7f3f416fcf17 in _save_Materialfv ../src/mesa/vbo/vbo_save_api.c:1405 #1 0x7f3f418199de in _mesa_unmarshal_Materialfv src/mapi/glapi/gen/marshal_generated0.c:5006 #2 0x7f3f413c6863 in glthread_unmarshal_batch ../src/mesa/main/glthread.c:65 #3 0x7f3f4124d368 in util_queue_thread_func ../src/util/u_queue.c:309 #4 0x7f3f41391eba in impl_thrd_routine ../src/c11/impl/threads_posix.c:67 #5 0x7f3f4c619c6b in start_thread glibc-2.35/nptl/pthread_create.c:442 #6 0x7f3f4c69e1fb in __clone3 (/lib64/libc.so.6+0x10c1fb) 0x607000010024 is located 20 bytes inside of 80-byte region [0x607000010010,0x607000010060) freed by thread T6 here: #0 0x7f3f4f093b48 in __interceptor_realloc (/usr/lib64/libasan.so.6+0xb1b48) #1 0x7f3f416e5b0c in grow_vertex_storage ../src/mesa/vbo/vbo_save_api.c:417 #2 0x7f3f416e69bc in fixup_vertex ../src/mesa/vbo/vbo_save_api.c:1266 #3 0x7f3f416fb13e in _save_Materialfv ../src/mesa/vbo/vbo_save_api.c:1405 #4 0x7f3f418199de in _mesa_unmarshal_Materialfv src/mapi/glapi/gen/marshal_generated0.c:5006 #5 0x7f3f413c6863 in glthread_unmarshal_batch ../src/mesa/main/glthread.c:65 #6 0x7f3f4124d368 in util_queue_thread_func ../src/util/u_queue.c:309 #7 0x7f3f41391eba in impl_thrd_routine ../src/c11/impl/threads_posix.c:67 #8 0x7f3f4c619c6b in start_thread glibc-2.35/nptl/pthread_create.c:442 Signed-off-by:
Patrick Lerda <patrick9876@free.fr> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!21419>
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Now that all color blend bits are dynamic, emit_cb_state() is doing almost nothing and half of that is wrong. In the case that color write enable is dynamic, at the time the pipeline state is emitted, it sees all the color attachments as having write disabled and stores the WriteDisabled bit for each channel. When all dynamic state is flushed, we have the right values already but the values recorded into the command buffer get ORed with the ones stored in the pipeline, and so WriteDisabled tag along when they shouldn't. Since all disabled color attachments are handled already when dynamic state is flushed, there's no point in doing so at pipeline creation time too. And since the only other thing done by emit_cb_state() is writing three hardcoded values, they might as well be taken care of in the same place as everything else. Fixes CTS from the future: dEQP-VK.pipeline.*.extended_dynamic_state.*.color_blend_equation_*dynamic* dEQP-VK.pipeline.*.extended_dynamic_state.*.color_blend_all_* Fixes: fc3fd7c6 (anv: dynamic color write mask) Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by:
Tapani Pälli <tapani.palli@intel.com> Part-of: <mesa/mesa!21509>
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Fixes: fc3fd7c6 (anv: dynamic color write mask) Fixes: 9dc6bed9 (anv: dynamic state for logic op enable) Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by:
Tapani Pälli <tapani.palli@intel.com> Part-of: <mesa/mesa!21509>
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Fixes: 092be5a3 ("vulkan: Add more dynamic color blend states") Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by:
Tapani Pälli <tapani.palli@intel.com> Part-of: <mesa/mesa!21509>
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This will emulate VGT_ESGS_RING_ITEMSIZE, which does the multiplication for us. It's beneficial to stop setting VGT_ESGS_RING_ITEMSIZE to reduce context rolls, and also the register will be removed in the future. Reviewed-by:
Timur Kristóf <timur.kristof@gmail.com> Part-of: <mesa/mesa!21525>
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Reviewed-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <mesa/mesa!21525>
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For testing, the conformant behavior can be enabled by setting conformant_trunc_coord to true manually and running this to enable the conformant behavior in hw: umr -w *.*.regTA_CNTL2 0x40000 The layer index rounding and TRUNC_COORD resetting workarounds can disabled in the shader compiler. Reviewed-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <mesa/mesa!21525>
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This is an internal recommendation. Acked-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <mesa/mesa!21525>
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A hw guy told me this. Acked-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <mesa/mesa!21525>
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Reviewed-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <mesa/mesa!21525>
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Reviewed-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <mesa/mesa!21525>
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for better readability Reviewed-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <mesa/mesa!21525>
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Acked-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <mesa/mesa!21525>
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Fixes: a29218b5 - radeonsi/gfx11: always set MSAA_NUM_SAMPLES=0 for DCC_DECOMPRESS Closes: mesa/mesa#8261 Acked-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <mesa/mesa!21525>
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Reviewed-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <mesa/mesa!21525>
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Reviewed-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <mesa/mesa!21525>
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Reviewed-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <mesa/mesa!21525>
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LS_OUT_PATCH_SIZE limited the maximum value. Acked-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <mesa/mesa!21525>
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This became unused when we switched to nir_lower_hs_inputs_to_mem. Reviewed-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <mesa/mesa!21525>
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Gfx11 doesn't support legacy GS. Reviewed-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <mesa/mesa!21525>
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Reviewed-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <mesa/mesa!21525>
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Reviewed-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <mesa/mesa!21525>
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Reviewed-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <mesa/mesa!21525>
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use gfx11 names Acked-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <mesa/mesa!21525>
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Reviewed-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <mesa/mesa!21525>
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It will be remove completely in the next commit. Related: mesa/mesa#8176 Cc: mesa-stable Acked-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <mesa/mesa!21525>
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Reviewed-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <mesa/mesa!21525>
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Acked-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <mesa/mesa!21525>
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because they are all next to each other. Reviewed-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <mesa/mesa!21525>
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The value is the same, but LS_0 is for gfx9 only, and HS_0 is for everything except gfx9. Reviewed-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <mesa/mesa!21525>
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Reviewed-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <mesa/mesa!21525>
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Reviewed-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <mesa/mesa!21525>
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They can be set si_shader_ps. Reviewed-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <mesa/mesa!21525>
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Fixes: caa09f66 - amd: add chip identification for gfx1100-1103 Acked-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <mesa/mesa!21525>
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Fixes: 9fecac09 - radeonsi/gfx11: scattered register deltas Reviewed-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <mesa/mesa!21525>
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Fixes: 9fecac09 - radeonsi/gfx11: scattered register deltas Reviewed-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <mesa/mesa!21525>
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Reviewed-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <mesa/mesa!21525>
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Fixes: caa09f66 - amd: add chip identification for gfx1100-1103 Acked-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <mesa/mesa!21525>
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Fixes: e673bb4a - amd,util: fix how lod bias is converted to fixed-point Acked-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <mesa/mesa!21525>
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