The upstream Weston implementation has a limitation that the various DPMS modes could only be set across for all of the compositor's outputs and not exclusively for an individual output.
In IVI, there are several displays connected to a SoC. These displays are just driven by differential pairs (LVDS, FPD-Link, GMSL) and powered centrally. To reduce power comsumption when user inactivity timeout happended on the display, there is a need to cut down pixel clock from SoC. Then, if any input events happend on the display, it should become active again.
This needs to be improved so that Weston sets the DMPS mode only for the output requested by the user while all other compositor outputs remain unaffected.