- Aug 12, 2017
-
-
Emil Velikov authored
Signed-off-by:
Emil Velikov <emil.velikov@collabora.com>
-
- Aug 11, 2017
-
-
This seems like a workaround, but we don't see the bug on CIK/VI. On SI with the dEQP-VK.memory.pipeline_barrier.host_read_transfer_dst.* tests, when one tests complete, the first flush at the start of the next test causes a VM fault as we've destroyed the VM, but we end up flushing the compute shader then, and it must still be in the process of doing something. Could also be a kernel difference between SI and CIK. v2: hit this with a bigger hammer. This fixes a bunch of hangs in the vk cts with the robustness tests. Fixes: f4e499ec ("radv: add initial non-conformant radv vulkan driver") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101334 Acked-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by:
Dave Airlie <airlied@redhat.com> (cherry picked from commit 82ba384c)
-
This ports the workaround from radeonsi, that was missing in radv. This fixes Talos rendering when MSAA is enabled on my Tahiti card. Reviewed-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Fixes: f4e499ec (radv: add initial non-conformant radv vulkan driver) Signed-off-by:
Dave Airlie <airlied@redhat.com> (cherry picked from commit 8bf39307)
-
This just copies the code from the -pro shaders, and fixes the tests on CIK. With this CIK passes the same set of conformance tests as VI. Fixes: 83e58b03 (radv: flush f32->f16 conversion denormals to zero. (v2)) Reviewed-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by:
Dave Airlie <airlied@redhat.com> (cherry picked from commit 3f389f75)
-
The argument here is a bitmask, so the old code selected .xy, which got silently truncated to .x when constructing the vec4 from components, instead of using .w. Fixes: 588185eb "radv/meta: add srgb conversion to end of resolve shader." Reviewed-by:
Dave Airlie <airlied@redhat.com> (cherry picked from commit acba3a31)
-
It justs works with the fragment shader resolve, so no need to do a custom conversion. In fact with SRGB dest, it actually gives wrong results. Fixes: 69136f4e "radv/meta: add resolve pass using fragment/vertex shaders" Reviewed-by:
Dave Airlie <airlied@redhat.com> (cherry picked from commit 15e5a7a6)
-
These seem to store very bogus results. Luckily there is some code that converts srgb->linear already, so just making the descriptor format UNORM should work. Fixes: 588185eb "radv/meta: add srgb conversion to end of resolve shader." Reviewed-by:
Dave Airlie <airlied@redhat.com> (cherry picked from commit 8286c3a4)
-
This fixes corrupted shadows in Unigine Valley. The corruption disappeared when I stopped setting IMG_DATA_FORMAT_24_8 for depth. Cc: 17.2 <mesa-stable@lists.freedesktop.org> Reviewed-by:
Nicolai Hähnle <nicolai.haehnle@amd.com> (cherry picked from commit 27fef5d5)
-
Also, silence an obnoxious finishme that started occurring for all GL applications which use stencil after the i965 ISL conversion. v2: Check against 3DSTATE_STENCIL_BUFFER's pitch bits when using separate stencil, and 3DSTATE_DEPTH_BUFFER's bits when using combined depth-stencil. Cc: "17.2" <mesa-stable@lists.freedesktop.org> Reviewed-by:
Jason Ekstrand <jason@jlekstrand.net> (cherry picked from commit 5563872d)
-
Emil Velikov authored
If we have an invalid display fed into the functions, the display lookup will return NULL. Thus as we attempt to get the platform type, we'll deref. it leading to a crash. Keep in mind that this will not happen if Mesa is built without X11 or when the legacy eglCreate*Surface codepaths are used. A similar check was added with earlier commit 5e97b8f5 ("egl: Fix crashes in eglCreate*Surface), although it was only applicable when the surfaceless platform is built. Cc: mesa-stable@lists.freedesktop.org Signed-off-by:
Emil Velikov <emil.velikov@collabora.com> Reviewed-by:
Eric Engestrom <eric.engestrom@imgtec.com> Reviewed-by:
Tapani Pälli <tapani.palli@intel.com> (cherry picked from commit 26fbb9ea) [Emil Velikov: resolve trivial conflicts] Signed-off-by:
Emil Velikov <emil.velikov@collabora.com> Conflicts: src/egl/main/eglapi.c
-
Fixes "configure: line 27326: test: argument expected" CC: mesa-stable@lists.freedesktop.org Reviewed-by:
Matt Turner <mattst88@gmail.com> (cherry picked from commit 4d9b0dcc)
-
UE4Editor has this issue. This commit prevents hangs (release build) or assertion failures (debug build). It doesn't fix the editor, but catastrophic scenarios are prevented. Cc: 17.1 17.2 <mesa-stable@lists.freedesktop.org> Reviewed-by:
Michel Dänzer <michel.daenzer@amd.com> Reviewed-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> (cherry picked from commit 4630ede1)
-
For mul(a, +-1) codegen can generate OP_MOV with a saturation flag set which is ignored at emission. The same can happen with add(a, 0), and others. Adding an assert for detecting more of such issues. Fixes wrongly rendered water in Hitman Absolution running under wine. Also a few shaders in Mad Max and Alien Isolation produce such MOVs. CC: <mesa-stable@lists.freedesktop.org> Signed-off-by:
Karol Herbst <karolherbst@gmail.com> Reviewed-by:
Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de> [imirkin: generalize the fix for other cases] Reviewed-by:
Ilia Mirkin <imirkin@alum.mit.edu> (cherry picked from commit 24a799ad)
-
Need to take the sample count into account in the depth decompress and resummarize pipelines and render pass. Fixes: f4e499ec ("radv: add initial non-conformant radv vulkan driver") Signed-off-by:
Alex Smith <asmith@feralinteractive.com> Reviewed-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Cc: "17.2" <mesa-stable@lists.freedesktop.org> (cherry picked from commit 2e9a13bf)
-
Originally, I had moved it to the caller to make some things easier when adding the CCS modifier. However, this broke DRI2 because intel_process_dri2_buffer calls intel_miptree_create_for_bo but never calls intel_miptree_alloc_aux. Also, in hindsight, it should be pretty easy to make the CCS modifier stuff work even if create_for_bo allocates the CCS when DISABLE_AUX is not set. Reviewed-by:
Jordan Justen <jordan.l.justen@intel.com> Cc: "17.2" <mesa-stable@lists.freedesktop.org> (cherry picked from commit 8e5808fc) [Emil Velikov: resolve trivial conflicts] Signed-off-by:
Emil Velikov <emil.velikov@collabora.com> Conflicts: src/mesa/drivers/dri/i965/intel_mipmap_tree.c
-
We were calculating the total height of 2D surfaces by multiplying the row pitch by the number of slices. This means that we actually request slightly more space than actually needed since the padding on the last slice is unnecessary. For tiled surfaces this is not likely to make a difference. For linear surfaces, on the other hand, this means we may require additional memory. In particular, this makes the i965 driver reject EGL imports of buffers which do not have this extra padding. Reviewed-by:
Jordan Justen <jordan.l.justen@intel.com> Cc: "17.2" <mesa-stable@lists.freedesktop.org> (cherry picked from commit 4d27c609)
-
The docs contain a bunch of commentary about the need to pad various surfaces out to multiples of something or other. However, all of those requirements are about avoiding GTT errors due to missing pages when the data port or sampler accesses slightly out-of-bounds. However, because the kernel already fills all the empty space in our GTT with the scratch page, we never have to worry about faulting due to OOB reads. There are two caveats to this: 1) There is some potential for issues with caches here if extra data ends up in a cache we don't expect due to OOB reads. However, because we always trash the entire cache whenever we need to move anything between cache domains, this shouldn't be an issue. 2) There is a potential issue if a surface gets placed at the very top of the GTT by the kernel. In this case, the hardware could potentially end up trying to read past the top of the GTT. If it nicely wraps around at the 48-bit (or 32-bit) boundary, then this shouldn't be an issue thanks to the scratch page. If it doesn't, then we need to come up with something to handle it. Up until some of the GL move to ISL, having the padding code in there just caused us to harmlessly use a bit more memory in Vulkan. However, now that we're using ISL sizes to validate external dma-buf images, these padding requirements are causing us to reject otherwise valid images due to the size of the BO being too small. Acked-by:
Kenneth Graunke <kenneth@whitecape.org> Tested-by:
Tapani Pälli <tapani.palli@intel.com> Tested-by:
Tomasz Figa <tfiga@chromium.org> Reviewed-by:
Jordan Justen <jordan.l.justen@intel.com> Cc: "17.2" <mesa-stable@lists.freedesktop.org> (cherry picked from commit c15b92ce)
-
We can't sample from depth-stencil formats but on gen7 but we can sample from depth-only formats. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102024 Reviewed-by:
Juan A. Suarez Romero <jasuarez@igalia.com> Cc: mesa-stable@lists.freedesktop.org (cherry picked from commit 06d3115b)
-
This is a bug in the app, but I'd rather avoid hanging the GPU, esp if someone is running in validation and it takes out their development environment. v2: get it right, reverse the polarity. Reviewed-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Cc: <mesa-stable@lists.freedesktop.org> Signed-off-by:
Dave Airlie <airlied@redhat.com> (cherry picked from commit 36a1b613)
-
Emil Velikov authored
If we get a xfixes v1.x we'll error out, without freeing the xfixes_query reply. Cc: <mesa-stable@lists.freedesktop.org> Signed-off-by:
Emil Velikov <emil.velikov@collabora.com> Reviewed-by:
Eric Engestrom <eric.engestrom@imgtec.com> (cherry picked from commit c961b679)
-
- Aug 07, 2017
-
-
Emil Velikov authored
Signed-off-by:
Emil Velikov <emil.velikov@collabora.com>
-
- Aug 04, 2017
-
-
We don't want to advertise experimental extensions in actual releases. However, there's no harm in leaving the code lying around in the tree.
-
X/GLX can't handle them. This removes almost 500 GLX visuals that were incorrectly exposed. This is a less invasive version of Marek's .getCapability series. Note: the patch is not applicable for master, but only for the 17.2 branch. Suggested-by:
Marek Olšák <marek.olsak@amd.com> Signed-off-by:
Tomasz Figa <tfiga@chromium.org> CC: <mesa-stable@lists.freedesktop.org> Fixes: f33d8af7 "st/dri: add 32-bit RGBX/RGBA formats" [Emil Velikov: commit message polish] Reviewed-by:
Emil Velikov <emil.velikov@collabora.com>
-
Copy/paste error was duplicating a gen_knobs.cpp rule. Fixes: 5079c277 ("swr: [scons] Fix windows build") Reviewed-by:
Emil Velikov <emil.velikov@collabora.com> Reviewed-by:
Bruce Cherniak <bruce.cherniak@intel.com> (cherry picked from commit e4a6ae06)
-
Reported by valgrind at: glsl_to_tgsi_visitor::visit(ir_expression*) (st_glsl_to_tgsi.cpp:1560) When compiling the Deus Ex shaders. Fixes: 28a5e710 ("st/glsl_to_tgsi: handle precise modifier") Reviewed-by:
Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by:
Karol Herbst <karolherbst@gmail.com> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> (cherry picked from commit 06237fc9)
-
GLES/gl.h has historically provided some typedefs that are not used in the API itself. Restore these typedefs that were lost to avoid breaking applications. These seem to be the only typedefs removed in the update. Fixes: 7fd08177 "Update Khronos-supplied headers" [Eric: added a big warning to revert this patch when pulling the updated header] Signed-off-by:
Eric Engestrom <eric.engestrom@imgtec.com> (cherry picked from commit 3db05ed1)
-
This reverts commit 3008161d, which caused a regression for VMWare. The initial code had some recursion in it, that I removed by accident trying to add back the recursion broke lots of things, take the high road and revert for now. Fixes: 3008161d (st_glsl_to_tgsi: rewrite rename registers to use array fully.) Reviewed-by:
Brian Paul <brianp@vmware.com> Tested-by:
Brian Paul <brianp@vmware.com> Signed-off-by:
Dave Airlie <airlied@redhat.com> (cherry picked from commit b8bea9a0)
-
This fixes: dEQP-VK.api.copy_and_blit.core.blit_image.all_formats.* for a2r10g10b10 formats as destination on SI/CIK hardware. This adds support to the meta program for emitting 10-bit outputs, and adds 10-bit support to the fragment shader key. It also only does the int8/10 on SI/CIK. Fixes: f4e499ec (radv: add initial non-conformant radv vulkan driver) Reviewed-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by:
Dave Airlie <airlied@redhat.com> (cherry picked from commit df61a050)
-
In some APU situations the reported visible size can be larger than VRAM size. This properly clamps the value. Surprisingly both CTS and spec seem to allow a heap type with size 0, so this seemed like the easiest option to me. Signed-off-by:
Bas Nieuwenhuizen <basni@google.com> Fixes: 4ae84efb "radv: Use enum for memory heaps." Reviewed-by:
Dave Airlie <airlied@redhat.com> Reviewed-by:
Michel Dänzer <michel.daenzer@amd.com> Tested-by:
Michel Dänzer <michel.daenzer@amd.com> (cherry picked from commit 8229706a)
-
Commit bbc29393 didn't include osmesa state_tracker. This patch adds necessary initialization. Fixes crash in OSMesa initialization. Created-by:
Charmaine Lee <charmainel@vmware.com> Tested-by:
Bruce Cherniak <bruce.cherniak@intel.com> Reviewed-by:
Charmaine Lee <charmainel@vmware.com> Cc: 17.2 <mesa-stable@lists.freedesktop.org> (cherry picked from commit 9966c85e)
-
If dual object compile fails (as seems to happen with virgl a fair bit, and does piglit even have any tests for it?), we end up not restarting the pull params, so we call vec4_visitor::move_uniform_array_access_to_pull_constant a second time and it runs over the ends of the alloc. Fixes: tests/spec/glsl-1.50/execution/geometry/max-input-components.shader_test running inside virgl on ivybridge. Reviewed-by:
Kenneth Graunke <kenneth@whitecape.org> Cc: <mesa-stable@lists.freedesktop.org> Signed-off-by:
Dave Airlie <airlied@redhat.com> (cherry picked from commit 271fa3a6)
-
Remember to add the offset to the start of the buffer in the relocation or else we write 0xff into random bytes elsewhere. Reviewed-by:
Kenneth Graunke <kenneth@whitecape.org> Cc: mesa-stable@lists.freedesktop.org (cherry picked from commit fb63c43f)
-
The cacheline alignment restriction is on the base address; the pitch can be anything. Fixes assertion failures when using primus (say, on glxgears, which creates a 300x300 linear BGRX surface with a pitch of 1200): intel_blit.c:190: get_blit_intratile_offset_el: Assertion `mt->surf.row_pitch % 64 == 0' failed. Cc: mesa-stable@lists.freedesktop.org Reviewed-by:
Chris Wilson <chris@chris-wilson.co.uk> (cherry picked from commit 595a47b8)
-
Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: "17.1 17.2" <mesa-stable@lists.freedesktop.org> (cherry picked from commit 95c6a974)
-
This implements a wait for glXWaitGL, glXCopySubBuffer, dri flush_front and creation of fake front until all pending SwapBuffers have been committed to hardware. Among other things this fixes piglit glx-copy-sub-buffers on dri3. Signed-off-by:
Thomas Hellstrom <thellstrom@vmware.com> Reviewed-by:
Brian Paul <brianp@vmware.com> Reviewed-by:
Sinclair Yeh <syeh@vmware.com> Reviewed-by:
Eric Anholt <eric@anholt.net> Cc: <mesa-stable@lists.freedesktop.org> (cherry picked from commit 185ef06f)
-
The issue here is that the immediate is treated as a 64-bit value, and fetching it does not work reliably with swizzles that are different from xy and zw. Cc: mesa-stable@lists.freedesktop.org Reviewed-by:
Marek Olšák <marek.olsak@amd.com> (cherry picked from commit da83687c)
-
This looks like it's supported since llvm 3.9 at least, so switch over radeonsi and radv to using it, -pro also uses this. We can now drop creating lds for these operations as the ds_swizzle operation doesn't actually write to lds at all. Acked-by:
Marek Olšák <marek.olsak@amd.com> (stable requested due to fixing radv CIK conformance tests) Cc: mesa-stable@lists.freedesktop.org Signed-off-by:
Dave Airlie <airlied@redhat.com> (cherry picked from commit cb6f16dc) [Emil Velikov: resolve trivial conflicts] Signed-off-by:
Emil Velikov <emil.velikov@collabora.com> Conflicts: src/amd/common/ac_nir_to_llvm.c
-
This makes it match radeonsi. The LLVM backend itself will emit the correct instruction, but LLVM might do incorrect optimizations since it thinks the output is undefined when the input is 0, even though it's not supposed to be. We really need a new intrinsic, or for the backend to become smarter and recognize this pattern. Cc: mesa-stable@lists.freedesktop.org Reviewed-by:
Bas Nieuwenhuizen <basni@google.com> (cherry picked from commit 6d731c56)
-
The optimizations are only valid for 32-bit integers. They were mistakenly firing for 64-bit integers as well. Cc: mesa-stable@lists.freedesktop.org Reviewed-by:
Matt Turner <mattst88@gmail.com> (cherry picked from commit de914615)
-
This reverts commit 5c124126. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101961 Cc: 17.2 <mesa-stable@lists.freedesktop.org> (cherry picked from commit d85802e5)
-