- May 25, 2023
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This should be set to the enum, ffmpeg has it wrong so far, but the sample decoder has it right. convert radv to the proper answer. Fixes: 1693c03a ("radv/video: add initial h264 decoder for VCN") Reviewed-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <mesa/mesa!23225>
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Needed for GL_AMD_pinned_memory & zero-copy support in opencl Part-of: <mesa/mesa!23199>
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Reviewed-by:
Dave Airlie <airlied@redhat.com> Part-of: <mesa/mesa!23221>
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I'm sure this was broken. Fixes: 1bf39b1f - ac,radeonsi: rework how scratch_waves is used and move it to ac_gpu_info.c Reviewed-by:
Dave Airlie <airlied@redhat.com> Part-of: <mesa/mesa!23221>
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Fixes: 96913bbf - ac/surface: force linear image layout for chips not supporting image opcodes Closes: mesa/mesa#9073 Reviewed-by:
Dave Airlie <airlied@redhat.com> Part-of: <mesa/mesa!23221>
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Vulkan says you can do things like image resolves or blits on transfer queues, but D3D only allows literal copies. We could try to emulate a Vulkan transfer-only queue backed by multiple D3D queues, where we use the copy queue when possible but fall back to compute when needed, but let's wait until there's a good reason to do that... Part-of: <!23218>
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Turns out there was a good reason for having both buffer count and desc_count. They served different purposes. Fixes: 8887852d ("dzn: Add some docs around descriptor sets and remove redundant/unused data") Part-of: <mesa/mesa!23218>
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Part-of: <!23218>
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Forcing bindless on is nice for apps that don't use EXT_descriptor_indexing, but for the CTS, whenever EXT_descriptor_indexing is supported, it's used. To be able to more thoroughly test the not-bindless path, add a debug flag to turn it off. Part-of: <!23218>
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pvr_gpu_upload() can't be used in the case of pvr_gpu_upload_usc() as it expects the source and destination buffers to be the same size. This isn't the case because pvr_gpu_upload_usc() adds some padding bytes to the size passed in by the caller. Fixes: 547a10f8 ("pvr: switch pvr_cmd_buffer_alloc_mem to use pvr_bo_suballoc") Signed-off-by:
Frank Binns <frank.binns@imgtec.com> Reviewed-by:
Karmjit Mahil <Karmjit.Mahil@imgtec.com> Part-of: <!23185>
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Part-of: <mesa/mesa!23154>
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Part-of: <!23154>
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Part-of: <!23154>
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- May 24, 2023
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Fixes: 68a926a1 ("glthread: set GL_OUT_OF_MEMORY if we fail to upload vertices") Signed-off-by:
Patrick Lerda <patrick9876@free.fr> Reviewed-by:
Tapani Pälli <tapani.palli@intel.com> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!23166>
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excluding: aco, radv, addrlib Reviewed-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Acked-by:
David Heidelberg <david.heidelberg@collabora.com> Acked-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <!23113>
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Part-of: <mesa/mesa!23215>
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Signed-off-by:
David Heidelberg <david.heidelberg@collabora.com> Part-of: <mesa/mesa!23211>
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Signed-off-by:
David Heidelberg <david.heidelberg@collabora.com> Part-of: <mesa/mesa!23211>
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Fixes: 03ba57c6 - mesa: extend _mesa_bind_vertex_buffer to take ownership of the buffer reference Reviewed-by:
Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com> Part-of: <mesa/mesa!23112>
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arb_pipeline_statistics_query-frag is passing now. VRS flat shading was the culprit and since smooth lines, it's disabled because gl_SampleMaskIn is read. Incredible. Signed-off-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <mesa/mesa!23212>
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Usually the register demand before an instruction would be considered part of the previous instruction, since it's not greater than the register demand for that previous instruction. Except, it can be greater in the case of an definition fixed to a non-killed operand: the RA needs to reserve space between the two instructions for the definition (containing a copy of the operand). fossil-db (navi21): Totals from 5 (0.00% of 135636) affected shaders: PreVGPRs: 35 -> 40 (+14.29%) Signed-off-by:
Rhys Perry <pendingchaos02@gmail.com> Reviewed-by:
Daniel Schürmann <daniel@schuermann.dev> Closes: mesa/mesa#8807 Part-of: <mesa/mesa!22446>
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Signed-off-by:
Rhys Perry <pendingchaos02@gmail.com> Reviewed-by:
Daniel Schürmann <daniel@schuermann.dev> Part-of: <mesa/mesa!22446>
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We make the compiler assume the worst possible case (it's not great because we have to burn 32 GRFs of potential input data) and then we push the actual value through push constants. This enables VK_EXT_gpl usage on zink, which causes two traces to change their results. Raven is an imperceptible change, blender has missing original pngs but looks plausible. Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by:
Emma Anholt <emma@anholt.net> Part-of: <mesa/mesa!22378>
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We need to do 3 things to accomplish this : 1. make all the register access consider the maximal case when unknown at compile time 2. move the clamping of load_per_vertex_input prior to lowering nir_intrinsic_load_patch_vertices_in (in the dynamic cases, the clamping will use the nir_intrinsic_load_patch_vertices_in to clamp), meaning clamping using derefs rather than lowered nir_intrinsic_load_per_vertex_input 3. in the known cases, lower nir_intrinsic_load_patch_vertices_in in NIR (so that the clamped elements still be vectorized to the smallest number of URB read messages) Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by:
Emma Anholt <emma@anholt.net> Part-of: <mesa/mesa!22378>
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this should fix some erroneous zsbuf invalidation Fixes: 215beee1 ("zink: more explicitly track/check rp optimizing per-context") Part-of: <mesa/mesa!23189>
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Fixes: 270f9c0b ("zink: add ZINK_DEBUG=flushsync") Part-of: <mesa/mesa!23189>
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Follow-on clean up after 01e9ee79 ("nir: Drop unused name from nir_ssa_dest_init"). The referenced argument no longer exists. Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by:
Faith Ekstrand <faith.ekstrand@collabora.com> Reviewed-by:
Rob Clark <robclark@freedesktop.org> Reviewed-by:
Jesse Natalie <jenatali@microsoft.com> Part-of: <mesa/mesa!23181>
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This contains a bugfix: execution scopes are now respected when combining barriers. Otherwise control barriers can disappear during combining, which is wrong. Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by:
Caio Oliveira <caio.oliveira@intel.com> Part-of: <mesa/mesa!23181>
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Absent any knowledge about the hardware, if the backend wants to combine barriers we should try to combine all barriers. Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by:
Caio Oliveira <caio.oliveira@intel.com> Part-of: <mesa/mesa!23181>
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nir_registers are only supposed to be used temporarily. They may be created by a producer, but then must be immediately lowered prior to optimizing the produced shader. They may be created internally by an optimization pass that doesn't want to deal with phis, but that pass needs to lower them back to phis immediately. Finally they may be created when going out-of-SSA if a backend chooses, but that has to happen late. Regardless, there should be no case where a backend sees a shader that comes in with nir_registers needing to be lowered. The two frontend producers of registers (tgsi_to_nir and mesa/st) both call nir_lower_regs_to_ssa to clean up as they should. Some backend (like intel) already depend on this behaviour. There's no need for other backends to call nir_lower_regs_to_ssa too. Drop the pointless calls as a baby step towards replacing nir_register. Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <mesa/mesa!23181>
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iris: Replace aperture_bytes by sram size in iris_resource_create_for_image() for PIPE_USAGE_STAGING All platforms supported by Iris will have aperture_bytes set as 4Gb. Also this value is not the actual aperture in i915, it actualy is the GGTT size. So here replacing it by the sram size, something that will vary depending in the amount of RAM available. This fix some tests with Xe KMD, as it is not setting aperture_bytes. And will not do that as there is no UAPI to fetch this information and it is not planned to it to Xe UAPI. Signed-off-by:
José Roberto de Souza <jose.souza@intel.com> Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Ack-by:
Rohan Garg <rohan.garg@intel.com> Part-of: <mesa/mesa!22969>
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disable_tmu_pipelining has been recently set to false on two strategies that should set it to true. Fixes the following CTS test: dEQP-VK.graphicsfuzz.spv-stable-maze-flatten-copy-composite Fixes: c950098a - broadcom/compiler: move buffer loads to lower register pressure Reviewed-by:
Iago Toral Quiroga <itoral@igalia.com> Part-of: <mesa/mesa!23207>
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Enables GL_INTEL_shader_integer_functions2 Part-of: <mesa/mesa!23197>
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Ideally we would like to trigger a compilation error like we do on v3dv (VK_ERROR_UNKNOWN). But with v3d we can't really do that, as this could happen on a draw call. Let's at least assert so debug builds stops at this point. Reviewed-by:
Iago Toral Quiroga <itoral@igalia.com> Part-of: <mesa/mesa!23203>
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Right now if we fail to register allocate, we return the qpu_insts that we had at that point, even if the driver can't really use it. Also v3dv_pipeline was already assuming that it would return NULL on failure, returning VK_ERROR_UNKNOWN on that case. This allows CTS tests with a lot of pressure, that regress now and then to not being able to allocate, to finish with an error, instead of blocking forever. For example: dEQP-VK.graphicsfuzz.spv-stable-maze-flatten-copy-composite Reviewed-by:
Iago Toral Quiroga <itoral@igalia.com> Part-of: <mesa/mesa!23203>
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Indeed, the locally allocated "stimg" reference was not freed on a specific code path. For instance, this issue is triggered on radeonsi or r600 with: "piglit/bin/egl-ext_egl_image_storage -auto -fbo" while setting GALLIUM_REFCNT_LOG=refcnt.log. Fixes: 6a3f5c65 ("mesa: simplify st_egl_image binding process for texture storage") Signed-off-by:
Patrick Lerda <patrick9876@free.fr> Reviewed-by:
Tapani Pälli <tapani.palli@intel.com> Part-of: <mesa/mesa!23165>
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Signed-off-by:
Eric Engestrom <eric@igalia.com> Reviewed-by:
Martin Roukala (né Peres) <martin.roukala@mupuf.org> Part-of: <!23206>
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We've been trying to get podman to output its progress while it downloads images so that we don't think it's stuck, but until we manage to do that, a longer timeout means fewer inaccurate timeouts. Signed-off-by:
Eric Engestrom <eric@igalia.com> Reviewed-by:
Daniel Stone <daniels@collabora.com> Reviewed-by:
Martin Roukala (né Peres) <martin.roukala@mupuf.org> Part-of: <!23206>
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This fixes an assert crash in UE4 when forcing the blit path for image copies, caused by an image copy of a small miplevel which pixel size is smaller than a single compressed block, leading to an empty blit region. Reviewed-by:
Alejandro Piñeiro <apinheiro@igalia.com> Part-of: <mesa/mesa!23180>
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