i965/gen6: Issue direct depth stall and flush after depth clear
instead of calling unconditionally brw_emit_mi_flush() which does: brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_CACHE_FLUSH | PIPE_CONTROL_RENDER_TARGET_FLUSH | PIPE_CONTROL_CS_STALL); brw_emit_pipe_control_flush(brw, PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | PIPE_CONTROL_CONST_CACHE_INVALIDATE); Signed-off-by:Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by:
Kenneth Graunke <kenneth@whitecape.org> Reviewed-by:
Jason Ekstrand <jason@jlekstrand.net> (cherry picked from commit 46b34689)
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