- Feb 05, 2019
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Dylan Baker authored
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Cc: Jason Ekstrand <jason@jlekstrand.net> Fixes: 927ba12b ("anv/tests: Adding test for the state_pool padding.") Signed-off-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Eric Engestrom <eric.engestrom@intel.com> Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com><Paste> Reviewed-by: Dylan Baker <dylan@pnwbakers.com> (cherry picked from commit 8943eb8f)
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sizeof counts the terminating null character as well, so that also contributed to the ID computed for the X11 atom. But the convention is for only the non-null characters to contribute to the atom ID. Fixes: 2e12fe42 "loader/dri3: Enable adaptive_sync via _VARIABLE_REFRESH property" Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Eric Anholt <eric@anholt.net> (cherry picked from commit c0a540f3)
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- Feb 04, 2019
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Transform feedback did not set correct SO_DECL.ComponentMask for varyings packed in VARYING_SLOT_PSIZ: gl_Layer - VARYING_SLOT_LAYER in VARYING_SLOT_PSIZ.y gl_ViewportIndex - VARYING_SLOT_VIEWPORT in VARYING_SLOT_PSIZ.z gl_PointSize - VARYING_SLOT_PSIZ in VARYING_SLOT_PSIZ.w Fixes: 36ee2fd6 "anv: Implement the basic form of VK_EXT_transform_feedback" Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (cherry picked from commit 64d3b148)
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Previously, we only applied the fix to shaders with a dispatch mode of SIMD8 but the code it relies on for SIMD16 mode only applies to SIMD16 instructions. If you have a SIMD8 instruction in a SIMD16 shader, neither would trigger and the restriction could still be hit. Fixes: 232ed898 "i965/fs: Register allocator shoudn't use grf127..." Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (cherry picked from commit b4f0d062)
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- Feb 01, 2019
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We need to initialize all fields in rs->prim explicitly while creating new rastpos stage. Fixes: bac85342 ("st/mesa: allow glDrawElements to work with GL_SELECT feedback") v2: Initializing all fields in rs->prim as per Ilia. Reviewed-by: Brian Paul <brianp@vmware.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> (cherry picked from commit 69d736b1)
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- Jan 31, 2019
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Reported by Coverity: in the case of unsupported modifier request, the code does not jump to the “fail” label to destroy the acquired resource. CID: 1435704 Signed-off-by: Ernestas Kulik <ernestas.kulik@gmail.com> Fixes: 45bb8f29 ("broadcom: Add V3D 3.3 gallium driver called "vc5", for BCM7268.") (cherry picked from commit 90458bef)
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One of the CTS cases tries to invalidate just stencil of packed depth/stencil, and we incorrectly lost the depth contents. Fixes dEQP-GLES3.functional.fbo.invalidate.whole.unbind_read_stencil Fixes: 0c42b5f3 ("mesa: wire up InvalidateFramebuffer") Reviewed-by: Marek Olšák <marek.olsak@amd.com> (cherry picked from commit db2ae511)
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Fixes: aa0fed10 freedreno: move ir3 to common location Signed-off-by: Rob Clark <robdclark@gmail.com> (cherry picked from commit 39cfdf99)
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Fixes: b4476138 freedreno: move drm to common location Reviewed-by: Eric Engestrom <eric.engestrom@intel.com> Signed-off-by: Rob Clark <robdclark@gmail.com> (cherry picked from commit e252656d)
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This fixes serious stuttering in Shadow Of The Tomb Raider. Fixes: 50fd253b ("radv/winsys: Add priority handling during submit.") Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (cherry picked from commit 9c762c01)
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Reported by Coverity: in the case where there exist hardware and non-hardware queries, the code does not jump to err_free_query and leaks the query. CID: 1430194 Signed-off-by: Ernestas Kulik <ernestas.kulik@gmail.com> Fixes: 9ea90ffb ("broadcom/vc4: Add support for HW perfmon") (cherry picked from commit f6e49d5a)
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Earlier commit addressed 7 of the 8 instances available. v2: Rebase patch back to master (by anholt) Cc: Carsten Haitzler (Rasterman) <raster@rasterman.com> Cc: Eric Anholt <eric@anholt.net> Fixes: 300d3ae8 ("vc4: Declare the cpu pointers as being modified in NEON asm.") Signed-off-by: Emil Velikov <emil.velikov@collabora.com> (cherry picked from commit 385843ac)
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- Jan 30, 2019
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Dylan Baker authored
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Dylan Baker authored
Android.mk and autotools disagree about where generated files should go, which wasn't a problem until we wanted to build a dist tarball. This corrects the problme by changing the output and include paths to be the same on android and autotools (meson already has the correct include path). Fixes: 7d7b3083 ("automake: Fix path to generated source")
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Dylan Baker authored
Fixes: e68777c8 ("autotools: Deprecate the use of autotools")
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Dylan Baker authored
It is currently impossible to build a dist tarball that works when SWR requires LLVM 6. To generate the tarball we'd need to configure with LLVM 6, which is fine. But to build the dist check we need LLVM 7, as RadeonSI and RadV require that version. Unfortunately the headers genererated with LLVM 6 don't compile with LLVM 7, the API has changed between the two versions. I weighed a couple of options here. One would be to ship an unbootstrapped tarball generated with meson. This would fix the issue by not bootstrapping, so whatever version of LLVM used would work because the SWR headers would be generated at compile time. Unfortunately this would involve some heavy modifications to the infastructure used to upload the tarballs, and I've decided not to persue this.
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- Jan 29, 2019
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Dylan Baker authored
Fixes: 6281f26f ("v3d: Add support for shader_image_load_store.") Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
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Dylan Baker authored
Fixes: b63a1f8e ("glsl: Create file to contain software fp64 functions") Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
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Dylan Baker authored
Fixes: b63a1f8e ("glsl: Create file to contain software fp64 functions") Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
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Matt Turner authored
Use the trick of adding and then subtracting 2**52 (52 is the number of explicit mantissa bits a double-precision floating-point value has) to implement round-to-even. Cuts the number of instructions on SKL of the piglit test fs-roundEven-double.shader_test from 109 to 21. Reviewed-by: Roland Scheidegger <sroland@vmware.com>
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Marek Olšák authored
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
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Emma Anholt authored
Noticed while looking at the gitlab-CI MR.
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This batch->cleared value is only used to decide to use sysmem rendering or not, so it should include any buffers that are affected by a clear. This is required because the a2xx fast clear doesn't work with sysmem rendering. The a22x "normal" clear path doesn't work with sysmem either. Signed-off-by: Jonathan Marek <jonathan@marek.ca>
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Depth can be used even when there is no restore/resolve of depth. This happens when the depth buffer is invalidated after rendering to avoid the resolve operation. Signed-off-by: Jonathan Marek <jonathan@marek.ca>
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Set dirty bits on invalidate to trigger invalidate logic in fd_draw_vbo. Also, resource_written for color needs to be after the invalidate logic. Signed-off-by: Jonathan Marek <jonathan@marek.ca>
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Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Eric Anholt <eric@anholt.net>
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Rob Clark authored
And before someone actually starts implementing DiscardFramebuffer() lets rework the interface to something that is actually usable. Signed-off-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net>
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This allows freedreno to be aware of the depth invalidate when flushing batches on flush_resource. AFAIK, the only other driver which might care about this change is vc4, where I think it should help by allowing the depth invalidate to work with GALLIUM_HUD. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Eric Anholt <eric@anholt.net>
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Check if a pixel format is supported by the Wayland servers gpu driver before exposing it to the client via wl_drm, so we avoid reporting formats to the client which the server gpu can't handle. Restrict this reporting to the new color depth 30 formats for now, as the ARGB/XRGB8888 and RGB565 formats are probably supported by every gpu under the sun. Atm. this is mostly useful to allow proper PRIME renderoffload for depth 30 formats on the typical Intel iGPU + NVidia dGPU "NVidia Optimus" laptop combo. Tested on Intel, AMD, NVidia with single-gpu setup and on a Intel + NVidia Optimus setup. Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> Reviewed-by: Adam Jackson <ajax@redhat.com> Reviewed-by: Daniel Stone <daniels@collabora.com>
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Support PRIME render offload between a Wayland server gpu and a Wayland client gpu with different channel ordering for their color formats, e.g., between Intel drivers which currently only support ARGB2101010 and XRGB2101010 import/display and nouveau which only supports ABGR2101010 rendering and display on nv-50 and later. In the wl_visuals table, we also store for each format an alternate sibling format which stores colors at the same precision, but with different channel ordering, e.g., ARGB2101010 <-> ABGR2101010. If a given client-gpu renderable format is not supported by the server for import, but the alternate format is supported by the server, expose the client-gpu renderable format as a valid EGLConfig to the client. At eglSwapBuffers time, during the blitImage() detiling blit from the client backbuffer to the linear buffer, the client format is converted to the server supported format. As we have to do a copy for PRIME anyway, this channel swizzling conversion comes essentially for free. Note that even if a server gpu in principle does support sampling from the clients native format, this conversion will be a performance advantage if it allows to convert to the servers preferred format for direct scanout, as the Wayland compositor may then be able to directly page-flip a fullscreen client wl_buffer onto the primary plane, or onto a hardware overlay plane, avoiding an extra data copy for desktop composition. Tested so far under Weston with: nouveau single-gpu, Intel single-gpu, AMD single-gpu, "Optimus" Intel server iGPU for display + NVidia client dGPU for rendering. v2: Implement minor review comments by Eric Engestrom: Add some comment and assert, and some style fixes for clarity. No functional change. Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> Reviewed-by: Adam Jackson <ajax@redhat.com> Reviewed-by: Daniel Stone <daniels@collabora.com>
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Faith Ekstrand authored
Surface reads don't need them because they just have the one address payload. With surface writes, on the other hand, we can put the address and the data in the different halves and avoid building the payload all together. The decrease in register pressure and added freedom in register allocation resulting from this change reduces spilling enough to improve the performance of one customer benchmark by about 2x. Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
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Faith Ekstrand authored
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
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Faith Ekstrand authored
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
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Faith Ekstrand authored
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
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Faith Ekstrand authored
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
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Faith Ekstrand authored
We're about to add some more if cases so let's have the giant re-indent in it's own patch to make review easier. Acked-by: Iago Toral Quiroga <itoral@igalia.com>
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Faith Ekstrand authored
These have clearly never seen any use.... On gen8, the bottom 4 bits are missing so we need to shift them off before we call set_bits and shift again when we get the bits. Found by inspection. Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
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