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  1. Mar 25, 2024
  2. Mar 24, 2024
  3. Feb 26, 2024
  4. Feb 24, 2024
    • Peter Maydell's avatar
      Merge tag 'pull-request-2024-02-23' of https://gitlab.com/thuth/qemu into staging · dd88d696
      Peter Maydell authored
      * m68k: Fix exception frame format for 68010
      * Add cdrom test for LoongArch virt machine
      * Fix qtests when using --without-default-devices
      * Enable -Wvla
      * Windows 32-bit removal
      * Silence warnings in the test-x86-cpuid-compat qtest
      
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      # gpg: Signature made Fri 23 Feb 2024 19:06:43 GMT
      # gpg:                using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5
      # gpg:                issuer "thuth@redhat.com"
      # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full]
      # gpg:                 aka "Thomas Huth <thuth@redhat.com>" [full]
      # gpg:                 aka "Thomas Huth <huth@tuxfamily.org>" [full]
      # gpg:                 aka "Thomas Huth <th.huth@posteo.de>" [unknown]
      # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3  EAB9 2ED9 D774 FE70 2DB5
      
      * tag 'pull-request-2024-02-23' of https://gitlab.com/thuth/qemu
      
      :
        target/i386: do not filter processor tracing features except on KVM
        .gitlab-ci.d/windows.yml: Remove shared-msys2 abstraction
        .gitlab-ci.d: Drop cross-win32-system job
        docs: Document that 32-bit Windows is unsupported
        meson: Enable -Wvla
        target/ppc/kvm: Replace variable length array in kvmppc_read_hptes()
        target/ppc/kvm: Replace variable length array in kvmppc_save_htab()
        tests: skip dbus-display tests that need a console
        tests/qtest: Fix boot-serial-test when using --without-default-devices
        tests/cdrom-test: Add cdrom test for LoongArch virt machine
        target/m68k: Fix exception frame format for 68010
      
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      dd88d696
  5. Feb 23, 2024
    • Peter Maydell's avatar
      Merge tag 'pull-ppc-for-9.0-20240224' of https://gitlab.com/npiggin/qemu into staging · 91e3bf2e
      Peter Maydell authored
      * Avocado tests for ppc64 to boot FreeBSD, run guests with emulated
        or nested hypervisor facilities, among other things.
      * Update ppc64 CPU defaults to Power10.
      * Add a new powernv10-rainier machine to better capture differences
        between the different Power10 systems.
      * Implement more device models for powernv.
      * 4xx TLB flushing performance and correctness improvements.
      * Correct gdb implementation to access some important SPRs.
      * Misc cleanups and bug fixes.
      
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      # gpg: Signature made Fri 23 Feb 2024 15:27:57 GMT
      # gpg:                using RSA key 4E437DDA56616F4329B0A79567B30276A8621CAE
      # gpg: Good signature from "Nicholas Piggin <npiggin@gmail.com>" [unknown]
      # gpg: WARNING: This key is not certified with a trusted signature!
      # gpg:          There is no indication that the signature belongs to the owner.
      # Primary key fingerprint: 4E43 7DDA 5661 6F43 29B0  A795 67B3 0276 A862 1CAE
      
      * tag 'pull-ppc-for-9.0-20240224' of https://gitlab.com/npiggin/qemu
      
      : (47 commits)
        target/ppc: optimise ppcemb_tlb_t flushing
        target/ppc: 440 optimise tlbwe TLB flushing
        target/ppc: 4xx optimise tlbwe_lo TLB flushing
        target/ppc: 4xx don't flush TLB for a newly written software TLB entry
        target/ppc: Factor out 4xx ppcemb_tlb_t flushing
        target/ppc: Fix 440 tlbwe TLB invalidation gaps
        target/ppc: Add SMT support to time facilities
        target/ppc: Implement core timebase state machine and TFMR
        ppc/pnv: Implement the ChipTOD to Core transfer
        ppc/pnv: Wire ChipTOD model to powernv9 and powernv10 machines
        ppc/pnv: Add POWER9/10 chiptod model
        target/ppc: Fix move-to timebase SPR access permissions
        target/ppc: Improve timebase register defines naming
        target/ppc: Rename TBL to TB on 64-bit
        target/ppc: Update gdbstub to read SPR's CFAR, DEC, HDEC, TB-L/U
        hw/ppc: N1 chiplet wiring
        hw/ppc: Add N1 chiplet model
        hw/ppc: Add pnv nest pervasive common chiplet model
        ppc/pnv: Test pnv i2c master and connected devices
        ppc/pnv: Add a pca9554 I2C device to powernv10-rainier
        ...
      
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      91e3bf2e
    • Nicholas Piggin's avatar
      target/ppc: optimise ppcemb_tlb_t flushing · 4acc505d
      Nicholas Piggin authored
      
      Filter TLB flushing by PID and mmuidx.
      
      Zoltan reports that, together with the previous TLB flush changes,
      performance of a sam460ex machine running 'lame' to convert a wav to
      mp3 is improved nearly 10%:
      
                        CPU time    TLB partial flushes  TLB elided flushes
      Before            37s         508238               7680722
      After             34s             73                  1143
      
      Tested-by: default avatarBALATON Zoltan <balaton@eik.bme.hu>
      Acked-by: default avatarCédric Le Goater <clg@kaod.org>
      Signed-off-by: default avatarNicholas Piggin <npiggin@gmail.com>
      4acc505d
    • Nicholas Piggin's avatar
      target/ppc: 440 optimise tlbwe TLB flushing · 1b72973d
      Nicholas Piggin authored
      
      Have 440 tlbwe flush only the range corresponding to the addresses
      covered by the software TLB entry being modified rather than the
      entire TLB. This matches what 4xx does.
      
      Tested-by: default avatarBALATON Zoltan <balaton@eik.bme.hu>
      Acked-by: default avatarCédric Le Goater <clg@kaod.org>
      Signed-off-by: default avatarNicholas Piggin <npiggin@gmail.com>
      1b72973d
    • Nicholas Piggin's avatar
      target/ppc: 4xx optimise tlbwe_lo TLB flushing · 2ab03484
      Nicholas Piggin authored
      
      Rather than tlbwe_lo always flushing all TCG TLBs, have it flush just
      those corresponding to the old software TLB, and only if it was valid.
      
      Tested-by: default avatarBALATON Zoltan <balaton@eik.bme.hu>
      Acked-by: default avatarCédric Le Goater <clg@kaod.org>
      Signed-off-by: default avatarNicholas Piggin <npiggin@gmail.com>
      2ab03484
    • Nicholas Piggin's avatar
      target/ppc: 4xx don't flush TLB for a newly written software TLB entry · 372dbdb9
      Nicholas Piggin authored
      
      BookE software TLB is implemented by flushing old translations from the
      relevant TCG TLB whenever software TLB entries change. This means a new
      software TLB entry should not have any corresponding cached TCG TLB
      translations, so there is nothing to flush. The exception is multiple
      software TLBs that cover the same address and address space, but that is
      a programming error and results in undefined behaviour, and flushing
      does not give an obviously better outcome in that case either.
      
      Remove the unnecessary flush of a newly written software TLB entry.
      
      Tested-by: default avatarBALATON Zoltan <balaton@eik.bme.hu>
      Acked-by: default avatarCédric Le Goater <clg@kaod.org>
      Signed-off-by: default avatarNicholas Piggin <npiggin@gmail.com>
      372dbdb9
    • Nicholas Piggin's avatar
      target/ppc: Factor out 4xx ppcemb_tlb_t flushing · c191ad77
      Nicholas Piggin authored
      
      Flushing the TCG TLB pages that cache a software TLB is a common
      operation, factor it into its own function.
      
      Tested-by: default avatarBALATON Zoltan <balaton@eik.bme.hu>
      Acked-by: default avatarCédric Le Goater <clg@kaod.org>
      Signed-off-by: default avatarNicholas Piggin <npiggin@gmail.com>
      c191ad77
    • Nicholas Piggin's avatar
      target/ppc: Fix 440 tlbwe TLB invalidation gaps · e8fe1411
      Nicholas Piggin authored
      
      The 440 tlbwe (write entry) instruction misses several cases that must
      flush the TCG TLB:
      
      - If the new size is smaller than the existing size, the EA no longer
        covered should be flushed. This looks like an inverted inequality
        test.
      - If the TLB PID changes.
      - If the TLB attr bit 0 (translation address space) changes.
      - If low prot (access control) bits change.
      
      Fix this by removing tricks to avoid TLB flushes, and just invalidate
      the TLB if any valid entry is being changed, similarly to 4xx.
      Optimisations will be introduced in subsequent changes.
      
      Tested-by: default avatarBALATON Zoltan <balaton@eik.bme.hu>
      Acked-by: default avatarCédric Le Goater <clg@kaod.org>
      Signed-off-by: default avatarNicholas Piggin <npiggin@gmail.com>
      e8fe1411
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