intel: Don't cross DWORD boundaries with byte scratch load/store
The back-end swizzles dwords so that our indirect scratch messages match the memory layout of spill/fill messages for better cache coherency. The swizzle happens at a DWORD granularity. If a read or write crosses a DWORD boundary, the first bit will get correctly swizzled but whatever piece lands in the next dword will not because the scatter instructions assume sequential addresses for all bytes. For DWORD writes, this is handled naturally as part of scalarizing. For smaller writes, we need to be sure that a single write never escapes a dword. Fixes: fd04f858 ("intel/nir: Don't try to emit vector load_scratch instructions") Closes: mesa/mesa#7364 Reviewed-by:Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <mesa/mesa!19580>