intel/fs: avoid cmod optimization on instruction with different write_mask
I've been running into failures with tests like : dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_4.samples_1.1d.frag With the load_global_const_block_intel NIR intrinsic, you can load a vec8/vec16 with a predicate. The predicate is correctly uniformized to feed into the SEND instruction's flag register. The problem is that a series of optimization first remove the find_live_channel and then changes the broadcast into a simple MOV instruction, on the assumption that the first channel is always active if there is not control flow. This is correct. But after that the cmod optimzation will remove this instruction : mov.nz.f0.0(16) null:D, vgrf16+0.0<0>:D NoMask because it seems to be equivalent to : cmp.g.f0.0(16) vgrf16:D, vgrf12:D, 63d In this case vgrf16 is the predicate to the load block SEND instruction. Since the execution mask is different between both, some of the channels of the SEND instruction end up not being loaded or loaded with the wrong predication and we end up with incorrect UBO data. Signed-off-by:Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: mesa-stable Reviewed-by:
Marcin Ślusarz <marcin.slusarz@intel.com> Reviewed-by:
Ian Romanick <ian.d.romanick@intel.com> Part-of: <mesa/mesa!20852> (cherry picked from commit a50d2fdb)
Loading
Please register or sign in to comment