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    gpu: ipu-v3: Do not wait for DMFC FIFO to clear when disabling DMFC channel · 448ae8ea
    Liu Ying authored and Philipp Zabel's avatar Philipp Zabel committed
    
    
    According to basic tests, it looks there is no issue if we don't wait for
    DMFC FIFO to clear when disabling DMFC channel.  NXP BSP doesn't do that,
    either.  This patch is needed to avoid the annoying warning caused by a
    timeout on waiting for the FIFO to clear after we add the new
    DRM_PLANE_COMMIT_NO_DISABLE_AFTER_MODESET flag to the imx-drm driver
    which changes the procedure to disable display channel slightly.
    
    Cc: Philipp Zabel <p.zabel@pengutronix.de>
    Cc: David Airlie <airlied@linux.ie>
    Cc: Russell King <linux@armlinux.org.uk>
    Cc: Peter Senna Tschudin <peter.senna@gmail.com>
    Cc: Lucas Stach <l.stach@pengutronix.de>
    Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
    Signed-off-by: default avatarLiu Ying <gnuiyl@gmail.com>
    Signed-off-by: default avatarPhilipp Zabel <p.zabel@pengutronix.de>
    448ae8ea