• Andrew Jeffery's avatar
    pinctrl: Add core support for Aspeed SoCs · 4d3d0e42
    Andrew Jeffery authored
    The Aspeed SoCs typically provide more than 200 pins for GPIO and other
    functions. The signal enabled on a pin is determined on a priority
    basis, where a given pin can provide a number of different signal types.
    In addition to the priority levels, the Aspeed pin controllers describe
    the signal active on a pin by compound logical expressions involving
    multiple operators, registers and bits. Some difficulty arises as a
    pin's function bit masks for each priority level are frequently not the
    same (i.e. we cannot just flip a bit to change from a high to low
    priority signal), or even in the same register(s). Some configuration
    bits affect multiple pins, while in other cases the signals for a bus
    must each be enabled individually.
    Together, these features give rise to some complexity in the
    implementation. A more complete description of the complexities is
    provided in the associated header file.
    The patch doesn't implement pinctrl/pinmux/pinconf for any particular
    Aspeed SoC, rather it adds the framework for defining pinmux
    Signed-off-by: default avatarAndrew Jeffery <andrew@aj.id.au>
    Reviewed-by: Joel Stanley's avatarJoel Stanley <joel@jms.id.au>
    Signed-off-by: Linus Walleij's avatarLinus Walleij <linus.walleij@linaro.org>
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