ac, radv: Lower tess and GS I/O in a new NIR pass, so backends don't have to deal with it

Major refactor of tessellation and GS I/O in RADV. I also plan to extend this to RadeonSI soon.

In a nutshell, basically all cross-stage I/O is lowered directly to memory access (VRAM or LDS) in a new NIR pass. The result is that both RADV/ACO and RADV/LLVM share the same logic. The new pass is written is such a manner that it can be added to RadeonSI in the future to de-duplicate even more code.

New NIR intrinsics are added in order to represent the necessary concepts in NIR. These intrinsics are implemented in both ACO and LLVM. Then the new lowerings are added, and RADV takes them into use. Finally, the old, now superfluous I/O code is deleted from both backends.