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anv, iris: Skip RT flush and PS Scoreboard stall

Sagar Ghuge requested to merge sagarghuge/mesa:wip/chicken3 into main

We can drop RT flush and PS Scoreboard stall if state cache perf fix disabled is set to 1. If bit is set RCC uses the sum of Binding Table Pointer and Binding Table Index as tag in state cache instead of just Binding Table Index.

This MR is WIP since the kernel needs a COMMON_SLICE_CHICKEN3 register to add to the whitelist.

I got a patch for it but I waiting for the perf number after dropping these stalls/flush.

Edited by Sagar Ghuge

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