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pan/mdg: Fix register allocation for 16b vectors

Boris Brezillon requested to merge bbrezillon/mesa:midgard-16b-vec-align into master

When using swizzles on 16bit vectors, the swizzle in one vec4(16b) nibble can't cross the nibble boundary. That means you can't have something like

mov r0.u16.xyz, r1.u16.zwe, #0

is not allowed.

Let's take this alignment constraint into account when allocating registers.

Edited by Boris Brezillon

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