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staging/20.1: fix displayable DCC on gfx10.3 (commit: amd/common: Cache intra-tile addresses for retile map)

(cherry-pick reason: This fixes displayable DCC corruption on gfx10.3, though the exact root cause is unknown)

However complicated DCC addressing is it is still based on tiles. If we have the intra-tile offsets + tile dimensions we can expand that to the full image ourselves.

Behavior around ~1080p on a 2500U:

old: 30-60 ms on every miss

new: 5 ms initally (miss in the tile cache) <0.5 ms afterwards

The most common case is that the tile cache only contains data for 2 tiles, which for Raven/Renoir/Navi14 will be 4 KiB each, so the size increase is fairly modest.

Reviewed-by: Marek Olšák Part-of: !5865 (merged) (cherry picked from commit a37aeb12)

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