intel: Delete hardcoded devinfo->urb.size values for Gen7+ (sans DG1).
On all Gen7+ platforms except DG1, the URB is a subsection of the configurable L3 cache, and so the size can vary. The size listed in the documentation on those platforms is an "example size", picked by calculating it based on an arbitrarily chosen L3 config.
Hardcoding a value for those platforms provides no value and only confuses people trying to fill out these tables when doing hardware enabling. anv and iris never use this field. i965 uses it to initialize brw->urb.size, but then updates that in update_urb_size() to be the correct value, so the initial value doesn't matter.
Delete the values for Gen7+ and update the comment accordingly.
Inspired by !4958 (closed).