intel: Restrict 512B pitch alignment to compressed dmabufs

What does this MR do and why?

CCS on gfx12 was originally implemented based on the understanding that the pitch always had to be 512B aligned. Upon further inspection, this seems to only be a requirement for displayable surfaces (see HSD 1209978227, Bspec 47709 and 49252). By restricting the alignment requirement to displayable surfaces, we reduce memory consumption and generally increase performance on A750:

There haven't been any issues observed with gfx125, but on gfx120 some piglit tests start to fail unless fast-clears are disabled when the pitch is unaligned.

Closes: #10740 (closed)

/cc @fjdegroo @tripzero @llandwerlin @shadeslayer @jxzgithub