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intel: add MI command write/read fencing

Lionel Landwerlin requested to merge llandwerlin/mesa:review/intel-mi-write-read-fencing into main

What does this MR do and why?

For performance reasons, the Xe KMD wants to enable a separate pipe for read & write operations in the MI commands, leading to a previous write operation not always completing before a later read operation.

This would wreck a bunch of things since we kind of expect write & read to be ordered.

This MR enables tracking in the mi_builder so that we don't have to replicate things in each driver.

Anv still has a few special cases where CS writes data pulled by internal shader so this is taken care of as well.

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