intel/isl: Add and use multi-engine surf usage bits
What does this MR do and why?
Add and use two new surf usage bits:
* ISL_SURF_USAGE_MULTI_ENGINE_SEQ_BIT: the surface may be accessed by
multiple engines, but not in parallel.
* ISL_SURF_USAGE_MULTI_ENGINE_PAR_BIT: the surface may be accessed by
multiple engines in parallel.
Both usages are not concerned with read-after-read access patterns.
Using these bits allows ISL to conditionally use Tile64 to account for
the CCS WA from HSD 22015614752. Apart from the potential space savings,
are three additional benefits of this approach:
1) CCS can now be used with miptails on gfx12.5 (though nothing makes
use of this today).
2) CCS can now be used with 3D depth/stencil surfaces in GL.
3) CCS can now be used with 3D depth/stencil surfaces in Vulkan when
apps only use a single queue.
Edited by Nanley Chery