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nir: add scan/reduce lowering

Alyssa Rosenzweig requested to merge alyssa/mesa:nir/scan-reduce into main

This is from NAK. It inherits the limtation that hardware subgroups are 32 threads, which is indeed the case on AGX as well as NVIDIA. (This could be generalized if there are other backends that want to use this.)

The main difference compared to the NAK pass is that this is generalized to take a filter for backends that only need a little bit of lowering, as a treat. AGX supports some scan/reduce instructions in hardware.

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