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RFC: radeonsi, frontends/va: do not set PIPE_FLUSH_ASYNC when there are external handles

Chia-I Wu requested to merge olv/mesa:gallium-va-external into main

What does this MR do and why?

We are exploring

  1. vaEndPicture,
  2. vaExportSurfaceHandle, and
  3. DMA_BUF_IOCTL_EXPORT_SYNC_FILE

sequence for explicit fencing. Assuming vaEndPicture is similar to glFlush for synchronizations, when there are external handles, vaEndPicture should flush without PIPE_FLUSH_ASYNC like what glFlush does.

Without this MR, step (3) can return a stub (signaled) fence if it happens before the async amdgpu_cs_submit_ib call.

For the same reason, it seems vaapi buffer sharing with another process can have sync issues on radeonsi. I didn't verify this though.

/cc @mareko, @robclark

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