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ir3: lower 64b registers before creating preamble

Job Noorman requested to merge jnoorman/mesa:ir3-lower-64b-preamble into main

ir3_nir_lower_preamble cannot handle 64b @load/store_preamble so we have to make sure ir3_nir_opt_preamble will never produce them. Up to now, nir_lower_locals_to_regs was run after preamble lowering so 64b locals could still be around when lowering the preamble. This patch moves running this pass, as well as ir3_nir_lower_64b_regs, to before the preamble lowering.

Fixed Piglit tests:

  • spec@arb_gpu_shader_fp64@execution@fs-indirect-temp-double-dst
  • spec@arb_gpu_shader_fp64@execution@built-in-functions@fs-frexp-dvec4-variable-index

This patch has no impact on shader-db.

Note: a few cleanup passes used to be run after nir_lower_locals_to_regs (nir_opt_algebraic, nir_opt_constant_folding) and after ir3_nir_lower_64b_regs (nir_lower_alu_to_scalar, nir_copy_prop). As far as I can tell, these are not necessary anymore when running the register lowering earlier so this patch removes them.

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